Re: [Qemu-devel] qemu-system-ppc broken ?

[Aurelien Jarno]

On Fri, Nov 07, 2008 at 04:16:12AM +0100, François Revol wrote:
> Just to let you know it seems the ppc target it broken as of r5643:
> 
> $ qemu-system-ppc -M prep -serial stdio -k fr -vnc :8 -hda generated-
> ppc-gcc4/haiku.image -cdrom generated-ppc-gcc4/haiku-boot-cd-ppc.iso
> /home/revol/devel/qemu/trunk/tcg/tcg.c:1356: tcg fatal error
> Abandon
> 
> (image isn't bootable yet but at least it didn't crash lots of revs
> before)
> 
> I'm on debian stable on x86.
> 

>From what I see, it has been broken in revision 5493. It seems that the
i386 TCG backend is not able to alloc/free a temp variable. The problem 
also occurs when in single step mode, when only *2* temp variables are
allocated. The x86-64 TCG backend is not affected.

The quick and dirty patch below is able to workaround the problem.

Any one has an idea what happens?

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a01ff89..f54225c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2588,52 +2588,42 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
 #define GEN_ST(width, opc, type)                                              \
 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
 {                                                                             \
-    TCGv EA = tcg_temp_new(TCG_TYPE_TL);                                      \
-    gen_addr_imm_index(EA, ctx, 0);                                           \
-    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx);       \
-    tcg_temp_free(EA);                                                        \
+    gen_addr_imm_index(cpu_T[0], ctx, 0);                                      
     \
+    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], cpu_T[0], ctx->mem_idx);      
 \
 }
 
 #define GEN_STU(width, opc, type)                                             \
 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
 {                                                                             \
-    TCGv EA;                                                                  \
     if (unlikely(rA(ctx->opcode) == 0)) {                                     \
         GEN_EXCP_INVAL(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    EA = tcg_temp_new(TCG_TYPE_TL);                                           \
     if (type == PPC_64B)                                                      \
-        gen_addr_imm_index(EA, ctx, 0x03);                                    \
+        gen_addr_imm_index(cpu_T[0], ctx, 0x03);                               
     \
     else                                                                      \
-        gen_addr_imm_index(EA, ctx, 0);                                       \
-    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx);           \
-    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
-    tcg_temp_free(EA);                                                        \
+        gen_addr_imm_index(cpu_T[0], ctx, 0);                                  
     \
+    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], cpu_T[0], ctx->mem_idx);      
     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                        
     \
 }
 
 #define GEN_STUX(width, opc2, opc3, type)                                     \
 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
 {                                                                             \
-    TCGv EA;                                                                  \
     if (unlikely(rA(ctx->opcode) == 0)) {                                     \
         GEN_EXCP_INVAL(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    EA = tcg_temp_new(TCG_TYPE_TL);                                           \
-    gen_addr_reg_index(EA, ctx);                                              \
-    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx);           \
-    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
-    tcg_temp_free(EA);                                                        \
+    gen_addr_reg_index(cpu_T[0], ctx);                                         
     \
+    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], cpu_T[0], ctx->mem_idx);      
     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                        
     \
 }
 
 #define GEN_STX(width, opc2, opc3, type)                                      \
 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
 {                                                                             \
-    TCGv EA = tcg_temp_new(TCG_TYPE_TL);                                      \
-    gen_addr_reg_index(EA, ctx);                                              \
-    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx);           \
-    tcg_temp_free(EA);                                                        \
+    gen_addr_reg_index(cpu_T[0], ctx);                                         
     \
+    gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], cpu_T[0], ctx->mem_idx);      
     \
 }
 
 #define GEN_STS(width, op, type)                                              \


-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   address@hidden         | address@hidden
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