Re: [Qemu-devel] PowerPC reset vector?

[Aurelien Jarno]

On Sun, Dec 07, 2008 at 02:58:40PM +0200, Blue Swirl wrote:
> Hi,
Hi!

> Currently PPC hard reset vector is 0xfffffffc for most cases. I can't
> find this vector in the few PPC docs I have. Instead all docs point to
> 0x00100 + base, where base can be 0xfff00000 or zero. Is the vector
> correct?

According to the PowerISA manual, the reset exception vector is the one
you define. However on power-up, the CPU does not jump to the reset
exception vector but instead:
- initialize msr
- empty all TLB
- create a boot TLB that maps the last 4kB page in the implemented
  effective storage address space that maps to the last 4kB page of the
  physical address space
- start execution of instruction at the last word address of the page
  mapped by the boot TLB entry.

> OHW seems to depend on this extra vector, so if we change it, there
> may need to be some kind of compatibility hacks to let it work.

OHW seems to follow exactly what is mapped in a real processor. OTOH, as
qemu and the firmware are coupled, we can probably decide that the
processor starts at the reset exception vector.

> Background: Laurent Vivier and I are trying to get OpenBIOS to work on PPC.

Nice work. I am following the progress on openbios-devel. How close are
you to have a basic version working?

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