Re: [Qemu-devel] SH: Add prefi, icbi, synco

[Aurelien Jarno]

On Thu, Dec 11, 2008 at 09:25:17PM +0300, Vladimir Prus wrote:
> 
> This is the repost of my eariler patch:
> 
>       http://thread.gmane.org/gmane.comp.emulators.qemu/31389
> 
> In this version, the new instructions are recognized only on
> SH4A.
> 
> - Volodya

Thanks, applied.

> From 47f4b541c79259579f921c1662bd86d102829d67 Mon Sep 17 00:00:00 2001
> From: Vladimir Prus <address@hidden>
> Date: Sat, 20 Sep 2008 21:07:34 +0400
> Subject: [PATCH] SH: Add prefi, icbi, synco
> To: address@hidden
> X-KMail-Transport: CodeSourcery
> X-KMail-Identity: 901867920
> 
>       * target-sh4/cpu.h (enum sh_features): New.
>       (CPUSH4State): New field features.
>       * target-sh4/translate.c (DisasContext): New
>       field features.
>       (sh4_def_t): New field features.
>       (cpu_sh4_init): Initialize env->features.
>       (_decode_opc): Handle
>       prefi, icbi, and synco.
>       (gen_intermediate_code_internal): Initialize ctx.features.
> ---
>  target-sh4/cpu.h       |    7 +++++++
>  target-sh4/translate.c |   20 ++++++++++++++++++++
>  2 files changed, 27 insertions(+), 0 deletions(-)
> 
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index bcf326c..a0108b4 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -89,6 +89,10 @@ typedef struct tlb_t {
>  
>  #define NB_MMU_MODES 2
>  
> +enum sh_features {
> +    SH_FEATURE_SH4A = 1,
> +};
> +
>  typedef struct CPUSH4State {
>      int id;                  /* CPU model */
>  
> @@ -113,6 +117,9 @@ typedef struct CPUSH4State {
>      /* float point status register */
>      float_status fp_status;
>  
> +    /* The features that we should emulate. See sh_features above.  */
> +    uint32_t features;
> +
>      /* Those belong to the specific unit (SH7750) but are handled here */
>      uint32_t mmucr;          /* MMU control register */
>      uint32_t pteh;           /* page table entry high register */
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 8ba7c8b..d38e95f 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -49,6 +49,7 @@ typedef struct DisasContext {
>      int memidx;
>      uint32_t delayed_pc;
>      int singlestep_enabled;
> +    uint32_t features;
>  } DisasContext;
>  
>  #if defined(CONFIG_USER_ONLY)
> @@ -206,6 +207,7 @@ typedef struct {
>      uint32_t pvr;
>      uint32_t prr;
>      uint32_t cvr;
> +    uint32_t features;
>  } sh4_def_t;
>  
>  static sh4_def_t sh4_defs[] = {
> @@ -227,6 +229,7 @@ static sh4_def_t sh4_defs[] = {
>       .pvr = 0x10300700,
>       .prr = 0x00000200,
>       .cvr = 0x71440211,
> +     .features = SH_FEATURE_SH4A,
>       },
>  };
>  
> @@ -271,6 +274,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
>      env = qemu_mallocz(sizeof(CPUSH4State));
>      if (!env)
>       return NULL;
> +    env->features = def->features;
>      cpu_exec_init(env);
>      sh4_translate_init();
>      env->cpu_model_str = cpu_model;
> @@ -1562,6 +1566,21 @@ static void _decode_opc(DisasContext * ctx)
>       return;
>      case 0x0083:             /* pref @Rn */
>       return;
> +    case 0x00d3:             /* prefi @Rn */
> +     if (ctx->features & SH_FEATURE_SH4A)
> +         return;
> +     else
> +         break;
> +    case 0x00e3:             /* icbi @Rn */
> +     if (ctx->features & SH_FEATURE_SH4A)
> +         return;
> +     else
> +         break;
> +    case 0x00ab:             /* synco */
> +     if (ctx->features & SH_FEATURE_SH4A)
> +         return;
> +     else
> +         break;
>      case 0x4024:             /* rotcl Rn */
>       {
>           TCGv tmp = tcg_temp_new();
> @@ -1805,6 +1824,7 @@ gen_intermediate_code_internal(CPUState * env, 
> TranslationBlock * tb,
>      ctx.delayed_pc = -1; /* use delayed pc from env pointer */
>      ctx.tb = tb;
>      ctx.singlestep_enabled = env->singlestep_enabled;
> +    ctx.features = env->features;
>  
>  #ifdef DEBUG_DISAS
>      if (loglevel & CPU_LOG_TB_CPU) {
> -- 
> 1.5.3.5
> 


-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
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