[Qemu-devel] [6032] target-ppc: fix mtfsb0 and mtfsb1

[Aurelien Jarno]

Revision: 6032
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6032
Author:   aurel32
Date:     2008-12-14 18:40:58 +0000 (Sun, 14 Dec 2008)

Log Message:
-----------
target-ppc: fix mtfsb0 and mtfsb1

Signed-off-by: Aurelien Jarno <address@hidden>

Modified Paths:
--------------
    trunk/target-ppc/helper.h
    trunk/target-ppc/op_helper.c
    trunk/target-ppc/translate.c

Modified: trunk/target-ppc/helper.h
===================================================================
--- trunk/target-ppc/helper.h   2008-12-14 18:40:49 UTC (rev 6031)
+++ trunk/target-ppc/helper.h   2008-12-14 18:40:58 UTC (rev 6032)
@@ -58,6 +58,7 @@
 #endif
 DEF_HELPER_2(compute_fprf, i32, i64, i32)
 DEF_HELPER_2(store_fpscr, void, i64, i32)
+DEF_HELPER_1(fpscr_clrbit, void, i32)
 DEF_HELPER_1(fpscr_setbit, void, i32)
 DEF_HELPER_1(float64_to_float32, i32, i64)
 DEF_HELPER_1(float32_to_float64, i64, i32)

Modified: trunk/target-ppc/op_helper.c
===================================================================
--- trunk/target-ppc/op_helper.c        2008-12-14 18:40:49 UTC (rev 6031)
+++ trunk/target-ppc/op_helper.c        2008-12-14 18:40:58 UTC (rev 6032)
@@ -843,6 +843,24 @@
     set_float_rounding_mode(rnd_type, &env->fp_status);
 }
 
+void helper_fpscr_clrbit (uint32_t bit)
+{
+    int prev;
+
+    prev = (env->fpscr >> bit) & 1;
+    env->fpscr &= ~(1 << bit);
+    if (prev == 1) {
+        switch (bit) {
+        case FPSCR_RN1:
+        case FPSCR_RN:
+            fpscr_set_rounding_mode();
+            break;
+        default:
+            break;
+        }
+    }
+}
+
 void helper_fpscr_setbit (uint32_t bit)
 {
     int prev;

Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c        2008-12-14 18:40:49 UTC (rev 6031)
+++ trunk/target-ppc/translate.c        2008-12-14 18:40:58 UTC (rev 6032)
@@ -2355,11 +2355,14 @@
         gen_exception(ctx, POWERPC_EXCP_FPU);
         return;
     }
-    crb = 32 - (crbD(ctx->opcode) >> 2);
+    crb = 31 - crbD(ctx->opcode);
     gen_optimize_fprf();
     gen_reset_fpstatus();
-    if (likely(crb != 30 && crb != 29))
-        tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(1 << crb));
+    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
+        TCGv_i32 t0 = tcg_const_i32(crb);
+        gen_helper_fpscr_clrbit(t0);
+        tcg_temp_free_i32(t0);
+    }
     if (unlikely(Rc(ctx->opcode) != 0)) {
         tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
     }
@@ -2374,7 +2377,7 @@
         gen_exception(ctx, POWERPC_EXCP_FPU);
         return;
     }
-    crb = 32 - (crbD(ctx->opcode) >> 2);
+    crb = 31 - crbD(ctx->opcode);
     gen_optimize_fprf();
     gen_reset_fpstatus();
     /* XXX: we pretend we can only do IEEE floating-point computations */