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[Qemu-devel] [PATCH 24/42] target-ppc: add GEN_VXFORM_SIMM macro for sub


From: Nathan Froyd
Subject: [Qemu-devel] [PATCH 24/42] target-ppc: add GEN_VXFORM_SIMM macro for subsequent instructions.
Date: Sun, 14 Dec 2008 18:14:57 -0800

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-ppc/translate.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 33c9c40..20ebb10 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -374,6 +374,8 @@ EXTRACT_HELPER(IMM, 12, 8);
 EXTRACT_SHELPER(SIMM, 0, 16);
 /* 16 bits unsigned immediate value */
 EXTRACT_HELPER(UIMM, 0, 16);
+/* 5 bits signed immediate value */
+EXTRACT_HELPER(SIMM5, 16, 5);
 /* Bit count */
 EXTRACT_HELPER(NB, 11, 5);
 /* Shift count */
@@ -6295,6 +6297,22 @@ GEN_VXFORM(vrlw, 132);
 GEN_VXFORM(vsl, 452);
 GEN_VXFORM(vsr, 708);
 
+#define GEN_VXFORM_SIMM(name, xo)                                       \
+    GEN_HANDLER(name, 0x04, (xo >> 1) & 0x1f, (xo >> 6) & 0x1f, 0x00000000, 
PPC_ALTIVEC) \
+    {                                                                   \
+        TCGv_ptr rd;                                                    \
+        TCGv_i32 simm;                                                  \
+        if (unlikely(!ctx->altivec_enabled)) {                          \
+            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
+            return;                                                     \
+        }                                                               \
+        simm = tcg_const_i32(SIMM5(ctx->opcode));                       \
+        rd = gen_avr_ptr(rD(ctx->opcode));                              \
+        gen_helper_##name (rd, simm);                                   \
+        tcg_temp_free_i32(simm);                                        \
+        tcg_temp_free(rd);                                              \
+    }
+
 #define GEN_VXRFORM1(opname, name, str, xo, rc)                         \
     GEN_HANDLER2(name, str, 0x4, (xo >> 1) & 0x1f, ((xo >> 6) & 0x1f) | (rc << 
4), 0x00000000, PPC_ALTIVEC) \
     {                                                                   \
-- 
1.6.0.5





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