[Qemu-devel] [6233] target-mips: CP0 Random register improvements

[Aurelien Jarno]

Revision: 6233
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6233
Author:   aurel32
Date:     2009-01-08 18:48:12 +0000 (Thu, 08 Jan 2009)

Log Message:
-----------
target-mips: CP0 Random register improvements

- Use a LFSR to generate the random value
- Make sure to not return the same value twice

Based on a patch by Herv?\195?\169 Poussineau.

Signed-off-by: Aurelien Jarno <address@hidden>

Modified Paths:
--------------
    trunk/hw/mips_timer.c

Modified: trunk/hw/mips_timer.c
===================================================================
--- trunk/hw/mips_timer.c       2009-01-08 16:01:33 UTC (rev 6232)
+++ trunk/hw/mips_timer.c       2009-01-08 18:48:12 UTC (rev 6233)
@@ -7,10 +7,15 @@
 /* XXX: do not use a global */
 uint32_t cpu_mips_get_random (CPUState *env)
 {
-    static uint32_t seed = 0;
+    static uint32_t lfsr = 1;
+    static uint32_t prev_idx = 0;
     uint32_t idx;
-    seed = seed * 314159 + 1;
-    idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+    /* Don't return same value twice, so get another value */
+    do {
+        lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
+        idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+    } while (idx == prev_idx);
+    prev_idx = idx;
     return idx;
 }