[Qemu-devel] 4xx booting into Linux userspace

[Andrew May]

Thanks for including my last patch. And please CC me since I am not on
the list.

I finally got a 405 linux kernel booted into userspace.
The op_helper change is pretty straight forward, where the "tlb->attr"
values should have been set from the tlbwe_lo function instead of the
high function.
I am not sure that the tlb->attr bits completely line up with the
tlbwe_lo bits, since I don't know how else they are used besides the
zone bits.

For the helper.c I am not sure on the best way to deal with things.
The first change should be ok, where the zone mapping was just off.
But the other part where the 405 SPR doesn't seem to match up with
SPR's used in the core TLB lookup code.

But with these changes I am able to get to userspace login prompt.

===========================================================
diff --git a/trunk/target-ppc/op_helper.c b/trunk/target-ppc/op_helper.c
index a3392b1..bbfde68 100644
--- a/trunk/target-ppc/op_helper.c
+++ b/trunk/target-ppc/op_helper.c
@@ -3765,7 +3765,6 @@ void helper_4xx_tlbwe_hi (target_ulong entry, 
target_ulong val)
         cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
     }
     tlb->PID = env->spr[SPR_40x_PID]; /* PID */
-    tlb->attr = val & 0xFF;
 #if defined (DEBUG_SOFTWARE_TLB)
     if (loglevel != 0) {
         fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
@@ -3803,6 +3802,7 @@ void helper_4xx_tlbwe_lo (target_ulong entry, 
target_ulong val)
     entry &= 0x3F;
     tlb = &env->tlb[entry].tlbe;
     tlb->RPN = val & 0xFFFFFC00;
+    tlb->attr = val & 0xFF;
     tlb->prot &= ~(PAGE_EXEC | PAGE_WRITE);
     tlb->prot |= PAGE_READ;
     if (val & 0x200)

diff --git a/trunk/target-ppc/helper.c b/trunk/target-ppc/helper.c
index a953e1f..4148a4d 100644
--- a/trunk/target-ppc/helper.c
+++ b/trunk/target-ppc/helper.c
@@ -1222,11 +1222,13 @@ static int mmu40x_get_physical_address (CPUState *env, 
mmu_ctx_t *ctx,
                              env->spr[SPR_40x_PID], 0, i) < 0)
             continue;
         zsel = (tlb->attr >> 4) & 0xF;
-        zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
+        zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
 #if defined (DEBUG_SOFTWARE_TLB)
         if (loglevel != 0) {
-            fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
-                    __func__, i, zsel, zpr, rw, tlb->attr);
+            fprintf(logfile, "%s: Addr %08x TLB %d zsel %d zpr %d Z %08x rw %d 
attr %08x "
+                    "AT %d prot %04x PR %d\n",
+                    __func__, address, i, zsel, zpr, env->spr[SPR_40x_ZPR], 
rw, tlb->attr,
+                    access_type, tlb->prot, pr );
         }
 #endif
         /* Check execute enable bit */
@@ -2204,15 +2206,21 @@ static always_inline void powerpc_excp (CPUState *env,
         }
         goto store_next;
     case POWERPC_EXCP_DSI:       /* Data storage exception                   */
-#if defined (DEBUG_EXCEPTIONS)
+#if 1 || defined (DEBUG_EXCEPTIONS)
         if (loglevel != 0) {
-            fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
-                    env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+            fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX
+                    " Vecotor " ADDRX " NIP " ADDRX "\n",
+                    env->spr[SPR_DSISR], env->spr[SPR_DAR],
+                    env->excp_vectors[excp],
+                    env->nip );
         }
 #endif
         new_msr &= ~((target_ulong)1 << MSR_RI);
         if (lpes1 == 0)
             new_msr |= (target_ulong)MSR_HVB;
+        /*Not sure why this isn't the same */
+        env->spr[SPR_40x_DEAR] = env->spr[SPR_DAR];
+        env->spr[SPR_40x_ESR] = 0x00800000;
         goto store_next;
     case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
 #if defined (DEBUG_EXCEPTIONS)