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Re: [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions |
Date: |
Wed, 4 Feb 2009 11:39:36 +0100 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
On Thu, Jan 22, 2009 at 12:44:08PM -0800, Nathan Froyd wrote:
> Do the computation in higher precision and check for invalid operation
> conditions.
>
> Signed-off-by: Nathan Froyd <address@hidden>
> ---
> target-ppc/helper.h | 2 +
> target-ppc/op_helper.c | 54
> ++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 1 +
> 3 files changed, 57 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index a5d1972..6f5d6a6 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -236,6 +236,8 @@ DEF_HELPER_3(vaddfp, void, avr, avr, avr)
> DEF_HELPER_3(vsubfp, void, avr, avr, avr)
> DEF_HELPER_3(vmaxfp, void, avr, avr, avr)
> DEF_HELPER_3(vminfp, void, avr, avr, avr)
> +DEF_HELPER_4(vmaddfp, void, avr, avr, avr, avr)
> +DEF_HELPER_4(vnmsubfp, void, avr, avr, avr, avr)
>
> DEF_HELPER_1(efscfsi, i32, i32)
> DEF_HELPER_1(efscfui, i32, i32)
> diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
> index d952113..532a08a 100644
> --- a/target-ppc/op_helper.c
> +++ b/target-ppc/op_helper.c
> @@ -2223,6 +2223,29 @@ VCMP(gtsw, >, s32)
> #undef VCMP_DO
> #undef VCMP
>
> +void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
> + /* Need to do the computation in higher precision and round
> + * once at the end. */
> + float64 af, cf;
> + af = float32_to_float64(a->f[i], &env->vec_status);
> + cf = float32_to_float64(c->f[i], &env->vec_status);
> + if ((float64_is_infinity(af) && float64_is_zero(cf)) ||
> + (float64_is_zero(af) && float64_is_infinity(cf))) {
> + r->u32[i] = 0x7fc00000;
> + } else {
> + float64 t = float64_mul(af, cf, &env->vec_status);
> + float64 bf = float32_to_float64(b->f[i], &env->vec_status);
> + t = float64_add(t, bf, &env->vec_status);
> + r->f[i] = float64_to_float32(t, &env->vec_status);
> + }
> + }
> + }
> +}
The same way as for v{add,sub} I think the NaN part is already handled
by the softfloat code.
> +
> void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t
> *c)
> {
> int sat = 0;
> @@ -2460,6 +2483,37 @@ VMUL(uh, u16, u32)
> #undef VMUL_DO
> #undef VMUL
>
> +void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(r->f); i++) {
> + HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
> + /* Need to do the computation is higher precision and round
> + * once at the end. */
> + float64 af, cf;
> + af = float32_to_float64(a->f[i], &env->vec_status);
> + cf = float32_to_float64(c->f[i], &env->vec_status);
> + if ((float64_is_infinity(af) && float64_is_zero(cf)) ||
> + (float64_is_zero(af) && float64_is_infinity(cf))) {
> + r->u32[i] = 0x7fc00000;
> + } else {
> + float64 t = float64_mul(af, cf, &env->vec_status);
> + float64 bf = float32_to_float64(b->f[i], &env->vec_status);
> + if (unlikely(float64_is_infinity(t) &&
> + float64_is_infinity(bf) &&
> + float64_is_neg(t) == float64_is_neg(bf))) {
> + /* Magnitude subtraction of infinities */
> + r->u32[i] = 0x7fc00000;
> + } else {
> + t = float64_sub(t, bf, &env->vec_status);
> + t = float64_chs(t);
> + r->f[i] = float64_to_float32(t, &env->vec_status);
> + }
> + }
> + }
> + }
> +}
> +
Same here.
> void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> {
> ppc_avr_t result;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 6ff46e0..8b67333 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -6577,6 +6577,7 @@ GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
> GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
> GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
> GEN_VAFORM_PAIRED(vsel, vperm, 21)
> +GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
>
> /*** SPE extension
> ***/
> /* Register moves */
> --
> 1.6.0.5
>
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- Re: [Qemu-devel] [PATCH 08/14] Add vmaddfp and vnmsubfp instructions,
Aurelien Jarno <=