Re: [Qemu-devel] [5849] Change MMIO callbacks to use offsets, not absolute addresses.

[Blue Swirl]

On 2/25/09, Paul Brook <address@hidden> wrote:
> > > Bits of both. The TLB is tightly tied into the code generator. Once we
>  > > get out of the first-level TLB lookup you've not got anywhere near enough
>  > > information to be able to restore the CPU state. The only way to raise
>  > > exceptions from within an IO handler is to sync CPU state before every
>  > > memory access, and you really don't want to do that. This is why the
>  > > existing unassigned access fault code is busted.
>  >
>  > But because of possible MMU and unaligned access faults we already
>  > save PC and NPC (not in all cases).  Handling of those faults works,
>  > it's really needed for correct operation. For some faults PC/NPC save
>  > is not necessary, the fault handler can calculate env->pc from host
>  > PC. Why would the unassigned fault be different?
>
>
> I'm not sure how I can be any clearer.
>
>  You either have to explicitly sync state (In teh case of SPARC this means
>  saving PC and NPC), or you have to know about the fault in the low-level TLB
>  processing code where you still have enough information to recover this
>  information. Once you get into an IO handler you've no way of figuring out
>  what the current CPU state is. The "not in all cases"/"some faults" you
>  mention above is relatively rare instructions that may fault v.s. every
>  memory access.

Well, until r4431 we always saved PC and NPC for all memory access
instructions, but with that commit, some of the checks could be
removed and everything still work.

http://svn.savannah.gnu.org/viewvc?view=rev&root=qemu&revision=4431

I'm pretty sure that the instructions without checks generate faults
successfully, and also the 64/128 bit instructions where the checks
remain didn't work with the checks removed. And it was not possible to
remove the checks or state saving without the cpu_restore_state2 by
Fabrice. This area is still a bit murky for me.