[Qemu-devel] [6666] SH: Implement MOVCO.L and MOVLI.L

[Aurelien Jarno]

Revision: 6666
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6666
Author:   aurel32
Date:     2009-03-02 17:13:21 +0000 (Mon, 02 Mar 2009)
Log Message:
-----------
SH: Implement MOVCO.L and MOVLI.L

* target-sh4/cpu.h (struct CPUSH4State): New field ldst.
* target-sh4/translate.c (cpu_ldst): New.
  (sh4_translate_init): Initialize cpu_ldst.
  (_decode_opc): Support MOVCO.L and MOVLI.L.

(Vladimir Prus)

Modified Paths:
--------------
    trunk/target-sh4/cpu.h
    trunk/target-sh4/translate.c

Modified: trunk/target-sh4/cpu.h
===================================================================
--- trunk/target-sh4/cpu.h      2009-03-02 17:10:47 UTC (rev 6665)
+++ trunk/target-sh4/cpu.h      2009-03-02 17:13:21 UTC (rev 6666)
@@ -140,6 +140,8 @@
     uint32_t prr;              /* Processor Revision Register */
     uint32_t cvr;              /* Cache Version Register */
 
+    uint32_t ldst;
+
      CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
     tlb_t itlb[ITLB_SIZE];     /* instruction translation table */
     void *intc_handle;

Modified: trunk/target-sh4/translate.c
===================================================================
--- trunk/target-sh4/translate.c        2009-03-02 17:10:47 UTC (rev 6665)
+++ trunk/target-sh4/translate.c        2009-03-02 17:13:21 UTC (rev 6666)
@@ -72,7 +72,7 @@
 static TCGv cpu_gregs[24];
 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
-static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
+static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;
 static TCGv cpu_fregs[32];
 
 /* internal register indexes */
@@ -144,6 +144,8 @@
     cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
                                            offsetof(CPUState, delayed_pc),
                                            "_delayed_pc_");
+    cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
+                                     offsetof(CPUState, ldst), "_ldst_");
 
     for (i = 0; i < 32; i++)
         cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
@@ -1559,6 +1561,37 @@
     case 0x0029:               /* movt Rn */
        tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
        return;
+    case 0x0073:
+        /* MOVCO.L
+              LDST -> T
+               If (T == 1) R0 -> (Rn)
+               0 -> LDST
+        */
+        if (ctx->features & SH_FEATURE_SH4A) {
+           int label = gen_new_label();
+           gen_clr_t();
+           tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
+           tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
+           tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
+           gen_set_label(label);
+           tcg_gen_movi_i32(cpu_ldst, 0);
+           return;
+       } else
+           break;
+    case 0x0063:
+        /* MOVLI.L @Rm,R0
+               1 -> LDST
+               (Rm) -> R0
+               When interrupt/exception
+               occurred 0 -> LDST
+        */
+       if (ctx->features & SH_FEATURE_SH4A) {
+           tcg_gen_movi_i32(cpu_ldst, 0);
+           tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
+           tcg_gen_movi_i32(cpu_ldst, 1);
+           return;
+       } else
+           break;
     case 0x0093:               /* ocbi @Rn */
        {
            TCGv dummy = tcg_temp_new();