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[Qemu-devel] [PATCH 09/24] Split cpu_mmu_index into cpu_mmu_index_data a
From: |
Tristan Gingold |
Subject: |
[Qemu-devel] [PATCH 09/24] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code. |
Date: |
Thu, 19 Mar 2009 15:35:41 +0100 |
This is required by alpha system emulation as PAL mode disable instruction
mmu but not data mmu.
This might also be required for other cpus that have a split I/D mmu enable.
Signed-off-by: Tristan Gingold <address@hidden>
---
exec-all.h | 2 +-
softmmu_header.h | 4 ++--
target-alpha/cpu.h | 13 +++++++++++--
target-alpha/op_helper.c | 4 ++--
target-arm/cpu.h | 3 ++-
target-cris/cpu.h | 3 ++-
target-cris/translate.c | 6 +++---
target-i386/cpu.h | 3 ++-
target-m68k/cpu.h | 3 ++-
target-mips/cpu.h | 3 ++-
target-ppc/cpu.h | 3 ++-
target-sh4/cpu.h | 3 ++-
target-sparc/cpu.h | 3 ++-
target-sparc/translate.c | 2 +-
14 files changed, 36 insertions(+), 19 deletions(-)
diff --git a/exec-all.h b/exec-all.h
index 143aca1..a661cb1 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -318,7 +318,7 @@ static inline target_ulong get_phys_addr_code(CPUState
*env1, target_ulong addr)
int mmu_idx, page_index, pd;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- mmu_idx = cpu_mmu_index(env1);
+ mmu_idx = cpu_mmu_index_code(env1);
if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
(addr & TARGET_PAGE_MASK))) {
ldub_code(addr);
diff --git a/softmmu_header.h b/softmmu_header.h
index a1b3808..f6f83da 100644
--- a/softmmu_header.h
+++ b/softmmu_header.h
@@ -46,12 +46,12 @@
#elif ACCESS_TYPE == (NB_MMU_MODES)
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
+#define CPU_MMU_INDEX (cpu_mmu_index_data(env))
#define MMUSUFFIX _mmu
#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
+#define CPU_MMU_INDEX (cpu_mmu_index_code(env))
#define MMUSUFFIX _cmmu
#else
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 3e00507..5add698 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -297,16 +297,25 @@ struct CPUAlphaState {
#define cpu_exec cpu_alpha_exec
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler
+#define cpu_list alpha_cpu_list
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _executive
#define MMU_MODE2_SUFFIX _supervisor
#define MMU_MODE3_SUFFIX _user
+#define MMU_MODE4_SUFFIX _pal
+#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
-static inline int cpu_mmu_index (CPUState *env)
+#define MMU_PAL_IDX 4
+static inline int cpu_mmu_index_data (CPUState *env)
{
- return (env->ps >> 3) & 3;
+ return env->mmu_data_index;
+}
+
+static inline int cpu_mmu_index_code (CPUState *env)
+{
+ return env->mmu_code_index;
}
#if defined(CONFIG_USER_ONLY)
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 4015d4a..8ce1065 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1049,7 +1049,7 @@ uint64_t helper_ld_virt_to_phys (uint64_t virtaddr)
int index, mmu_idx;
void *retaddr;
- mmu_idx = cpu_mmu_index(env);
+ mmu_idx = cpu_mmu_index_data(env);
index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
redo:
tlb_addr = env->tlb_table[mmu_idx][index].addr_read;
@@ -1071,7 +1071,7 @@ uint64_t helper_st_virt_to_phys (uint64_t virtaddr)
int index, mmu_idx;
void *retaddr;
- mmu_idx = cpu_mmu_index(env);
+ mmu_idx = cpu_mmu_index_data(env);
index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
redo:
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f98655f..c0cfb8d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -412,7 +412,8 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
}
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index e98a48d..807a55a 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -212,7 +212,8 @@ enum {
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return !!(env->pregs[PR_CCS] & U_FLAG);
}
diff --git a/target-cris/translate.c b/target-cris/translate.c
index d5fcb9e..20699e9 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -1104,7 +1104,7 @@ static inline void cris_prepare_jmp (DisasContext *dc,
unsigned int type)
static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index_data(dc->env);
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1117,7 +1117,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst,
TCGv addr)
static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size, int sign)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index_data(dc->env);
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1147,7 +1147,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv
addr,
static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index_data(dc->env);
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 90bceab..f3ccb53 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -842,7 +842,8 @@ static inline int cpu_get_time_fast(void)
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
}
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index e2529eb..94af716 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -218,7 +218,8 @@ void register_m68k_insns (CPUM68KState *env);
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return (env->sr & SR_S) == 0 ? 1 : 0;
}
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index cbf3cbd..c050bd0 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -489,7 +489,8 @@ void do_unassigned_access(target_phys_addr_t addr, int
is_write, int is_exec,
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return env->hflags & MIPS_HFLAG_KSU;
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 87b3460..4d75ced 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -809,7 +809,8 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn,
target_ulong val);
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _hypv
#define MMU_USER_IDX 0
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return env->mmu_idx;
}
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index aea7108..eaae3cf 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -181,7 +181,8 @@ void cpu_load_tlb(CPUSH4State * env);
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUState *env)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code (CPUState *env)
{
return (env->sr & SR_MD) == 0 ? 1 : 0;
}
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 8b84789..33cf4c3 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -456,7 +456,8 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo,
void *puc);
#define MMU_KERNEL_IDX 1
#define MMU_HYPV_IDX 2
-static inline int cpu_mmu_index(CPUState *env1)
+#define cpu_mmu_index_data cpu_mmu_index_code
+static inline int cpu_mmu_index_code(CPUState *env1)
{
#if defined(CONFIG_USER_ONLY)
return MMU_USER_IDX;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index d059408..017c375 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4769,7 +4769,7 @@ static inline void
gen_intermediate_code_internal(TranslationBlock * tb,
dc->pc = pc_start;
last_pc = dc->pc;
dc->npc = (target_ulong) tb->cs_base;
- dc->mem_idx = cpu_mmu_index(env);
+ dc->mem_idx = cpu_mmu_index_code(env);
dc->def = env->def;
if ((dc->def->features & CPU_FEATURE_FLOAT))
dc->fpu_enabled = cpu_fpu_enabled(env);
--
1.6.2
- [Qemu-devel] [PATCH 0/24]: add alpha es40 system emulation (v2), Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 01/24] Add support for multi-level phys map., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 02/24] Fix cpu_physical_memory_rw when operating on IO blocks., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 03/24] Fix bug: palcode is at least 6 bits., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 04/24] Fix bug: do not mask address LSBs for ldwu., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 05/24] bug fix: avoid nop to override next instruction, Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 06/24] Be slightly more verbose for unassigned_mem_read*, Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 07/24] Increase Alpha physical address size to 44 bits., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 08/24] Allow 5 mmu indexes., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 09/24] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code.,
Tristan Gingold <=
- [Qemu-devel] [PATCH 10/24] Add square wave output support., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 11/24] Add ali1543 super IO pci device., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 12/24] Add 21272 chipset (memory and pci controller for alpha), Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 13/24] Add target-alpha/machine.c and hw/es40.c for es40 machine emulation., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 14/24] Move softmmu_helper.h from exec.h to op_helper.c on alpha., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 15/24] Document which IPR are used by 21264., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 16/24] tb_flush helper should flush the tb (and not the tlb)., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 17/24] Add instruction name in comments for hw_ld opcode., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 18/24] Remove PALCODE_ declarations (unused)., Tristan Gingold, 2009/03/19
- [Qemu-devel] [PATCH 19/24] alpha ld helpers now directly return the value., Tristan Gingold, 2009/03/19