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[Qemu-devel] [RFC] [PATCH] tcg/x86_64: optimize register allocation orde
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [RFC] [PATCH] tcg/x86_64: optimize register allocation order |
Date: |
Sat, 28 Mar 2009 23:14:00 +0100 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
The beginning of the register allocation order list on the TCG x86_64
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always some registers to clobber.
The same way register %rsi and %rdi are at the top of the register
allocation order list, while they can't be used for load/store
operations. This means the data and/or address registers are very often
%rsi and %rdi, so a mov operation has to be inserted before and/or after
doing the load/store.
This patches changes to the allocation order to avoid those effects.
It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file,
and a 6% gain in qemu-system-mips64 to compile a small application.
Signed-off-by: Aurelien Jarno <address@hidden>
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index 92f0733..5378e85 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -44,22 +44,21 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#endif
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_RDI,
- TCG_REG_RSI,
- TCG_REG_RDX,
- TCG_REG_RCX,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_RAX,
- TCG_REG_R10,
- TCG_REG_R11,
-
TCG_REG_RBP,
TCG_REG_RBX,
TCG_REG_R12,
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R9,
+ TCG_REG_R8,
+ TCG_REG_RCX,
+ TCG_REG_RDX,
+ TCG_REG_RSI,
+ TCG_REG_RDI,
+ TCG_REG_RAX,
};
static const int tcg_target_call_iarg_regs[6] = {
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
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