[Qemu-devel] [7044] target-mips: optimize gen_flt3_ldst()

[Aurelien Jarno]

Revision: 7044
          http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=7044
Author:   aurel32
Date:     2009-04-08 21:48:10 +0000 (Wed, 08 Apr 2009)
Log Message:
-----------
target-mips: optimize gen_flt3_ldst()

Signed-off-by: Aurelien Jarno <address@hidden>

Modified Paths:
--------------
    trunk/target-mips/translate.c

Modified: trunk/target-mips/translate.c
===================================================================
--- trunk/target-mips/translate.c       2009-04-08 21:48:02 UTC (rev 7043)
+++ trunk/target-mips/translate.c       2009-04-08 21:48:10 UTC (rev 7044)
@@ -1124,7 +1124,7 @@
                           int base, int16_t offset)
 {
     const char *opn = "flt_ldst";
-    TCGv t0 = tcg_temp_local_new();
+    TCGv t0 = tcg_temp_new();
 
     if (base == 0) {
         tcg_gen_movi_tl(t0, offset);
@@ -7152,8 +7152,8 @@
 {
     const char *opn = "extended float load/store";
     int store = 0;
-    TCGv t0 = tcg_temp_local_new();
-    TCGv t1 = tcg_temp_local_new();
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
 
     if (base == 0) {
         gen_load_gpr(t0, index);
@@ -7165,6 +7165,7 @@
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
+    save_cpu_state(ctx, 0);
     switch (opc) {
     case OPC_LWXC1:
         check_cop1x(ctx);
@@ -7241,12 +7242,6 @@
         opn = "suxc1";
         store = 1;
         break;
-    default:
-        MIPS_INVAL(opn);
-        generate_exception(ctx, EXCP_RI);
-        tcg_temp_free(t0);
-        tcg_temp_free(t1);
-        return;
     }
     tcg_temp_free(t0);
     tcg_temp_free(t1);