[Qemu-devel] [PATCH 06/15] Peripheral driver for S3C SOC timers.

[Vincent Sanders]

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target     |    2 +-
 hw/s3c24xx_timers.c |  136 +++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 137 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_timers.c

diff --git a/Makefile.target b/Makefile.target
index f5594fb..2b35da7 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -674,7 +674,7 @@ OBJS+= omap_sx1.o palm.o tsc210x.o
 OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
-OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o
+OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
 OBJS+= framebuffer.o
 CPPFLAGS += -DHAS_AUDIO
 endif
diff --git a/hw/s3c24xx_timers.c b/hw/s3c24xx_timers.c
new file mode 100644
index 0000000..073c2f8
--- /dev/null
+++ b/hw/s3c24xx_timers.c
@@ -0,0 +1,136 @@
+/* hw/s3c24xx_timers.c
+ *
+ * Samsung S3C24XX emulation
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+#include "qemu-timer.h"
+
+#include "s3c24xx.h"
+
+/*
+  QEMU_TIMER_BASE is ticks per second for the qemu clocks
+  TCLK1 (assumed input for timer4) is 12 MHz
+  Thus, period in ticks of timer4 is:
+
+  (timer4_period * QEMU_TIMER_BASE) / TCLK1
+*/
+
+/* Timer configuration 0 */
+#define S3C_TIMERS_TCFG0 0
+/* Timer configuration 1 */
+#define S3C_TIMERS_TCFG1 1
+/* Timer control */
+#define S3C_TIMERS_TCON 2
+/* Timer count buffer 0 */
+#define S3C_TIMERS_TCNTB0 3
+/* Timer compare buffer 0 */
+#define S3C_TIMERS_TCMPB0 4
+/* Timer count observation 0 */
+#define S3C_TIMERS_TCNTO0 5
+/* Timer count buffer 1 */
+#define S3C_TIMERS_TCNTB1 6
+/* Timer compare buffer 1 */
+#define S3C_TIMERS_TCMPB1 7
+/* Timer count observation 1 */
+#define S3C_TIMERS_TCNTO1 8
+/* Timer count buffer 2 */
+#define S3C_TIMERS_TCNTB2 9
+/* Timer compare buffer 2 */
+#define S3C_TIMERS_TCMPB2 10
+/* Timer count observation 2 */
+#define S3C_TIMERS_TCNTO2 11
+/* Timer count buffer 3 */
+#define S3C_TIMERS_TCNTB3 12
+/* Timer compare buffer 3 */
+#define S3C_TIMERS_TCMPB3 13
+/* Timer count observation 3 */
+#define S3C_TIMERS_TCNTO3 14
+/* Timer count buffer 4 */
+#define S3C_TIMERS_TCNTB4 15
+/* Timer count observation 4 */
+#define S3C_TIMERS_TCNTO4 16
+
+static void
+s3c24xx_schedule_timer4(S3CState *soc)
+{
+    soc->timers_reg[S3C_TIMERS_TCNTB4] = soc->timer4_reload_value;
+    soc->timer4_last_ticked = qemu_get_clock(vm_clock);
+    qemu_mod_timer(soc->timer4,
+                   soc->timer4_last_ticked + ((soc->timer4_reload_value * 
ticks_per_sec) / soc->tclk1));
+}
+
+static void
+s3c24xx_timer4_tick(void *opaque)
+{
+    S3CState *soc = (S3CState *)opaque;
+
+    qemu_set_irq(soc->irqs[14], 1);
+    if (soc->timers_reg[S3C_TIMERS_TCON] && (1<<22)) {
+        s3c24xx_schedule_timer4(soc);
+    }
+}
+
+static void
+s3c24xx_timers_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int addr = (addr_ >> 2) & 0x1f;
+
+    soc->timers_reg[addr] = value;
+    if (addr == S3C_TIMERS_TCON) {
+        /* If Timer4's manual update is set, copy in the reload value */
+        if (value & (1 << 21) )
+            soc->timer4_reload_value = soc->timers_reg[S3C_TIMERS_TCNTB4];
+
+        /* If Timer4's manual update is unset, and the timer is running, start 
it */
+        if (!(value & (1 << 21)) &&
+            value & (1 << 20)) {
+            s3c24xx_schedule_timer4(soc);
+        }
+    }
+}
+
+static uint32_t
+s3c24xx_timers_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int addr = (addr_ >> 2) & 0x1f;
+
+    if (addr == S3C_TIMERS_TCNTO4 ) {
+        return soc->timer4_reload_value -
+            (((qemu_get_clock(vm_clock) - soc->timer4_last_ticked) * 
soc->tclk1) / ticks_per_sec);
+    }
+    return soc->timers_reg[addr];
+}
+
+
+static CPUReadMemoryFunc *s3c24xx_timers_read[] = {
+    &s3c24xx_timers_read_f,
+    &s3c24xx_timers_read_f,
+    &s3c24xx_timers_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_timers_write[] = {
+    &s3c24xx_timers_write_f,
+    &s3c24xx_timers_write_f,
+    &s3c24xx_timers_write_f,
+};
+
+void
+s3c24xx_timers_init(S3CState *soc, target_phys_addr_t base_addr)
+{
+    /* Samsung S3C2410X timer registration.
+     *
+     * Specifically the PWM timer4.
+     */
+    int tag = cpu_register_io_memory(0, s3c24xx_timers_read, 
s3c24xx_timers_write, soc);
+    cpu_register_physical_memory(base_addr, 17 * 4, tag);
+
+    soc->timer4 = qemu_new_timer(vm_clock, s3c24xx_timer4_tick, soc);
+}
-- 
1.5.4.3