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[Qemu-devel] [PATCH 14/15] S3C2440 Implementation using S3C periperals.


From: Vincent Sanders
Subject: [Qemu-devel] [PATCH 14/15] S3C2440 Implementation using S3C periperals.
Date: Wed, 6 May 2009 09:44:53 +0100

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target |    2 +-
 hw/s3c2440x.c   |  116 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/s3c2440x.h   |   30 ++++++++++++++
 3 files changed, 147 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c2440x.c
 create mode 100644 hw/s3c2440x.h

diff --git a/Makefile.target b/Makefile.target
index 4384d8c..b8074ad 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -677,7 +677,7 @@ OBJS+= musicpal.o pflash_cfi02.o
 OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
 OBJS+= s3c24xx_serial.o s3c24xx_rtc.o s3c24xx_gpio.o s3c24xx_iic.o
 OBJS+= s3c24xx_lcd.o s3c24xx_nand.o
-OBJS+= s3c2410x.o
+OBJS+= s3c2410x.o s3c2440x.o
 OBJS+= framebuffer.o
 CPPFLAGS += -DHAS_AUDIO
 endif
diff --git a/hw/s3c2440x.c b/hw/s3c2440x.c
new file mode 100644
index 0000000..d99b381
--- /dev/null
+++ b/hw/s3c2440x.c
@@ -0,0 +1,116 @@
+/* hw/s3c2440x.c
+ *
+ * Samsung S3C2440X emulation
+ *
+ * Copyright 2006, 2007 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c2440x.h"
+
+/* We use the PXA style OHCI USB mapping */
+#include "pxa.h"
+
+/* S3C2440 SoC IDs */
+#define CPU_S3C2440X_IDENT_S3C2440A 0x32440001
+
+/* Integrated SOC peripherals */
+
+/* SRAM */
+#define CPU_S3C2440X_SRAM_BASE (0x40000000)
+
+/* Memory control */
+#define CPU_S3C2440X_MEMC_BASE (0x48000000)
+
+/* USB controller */
+#define CPU_S3C2440X_OHCI (0x49000000)
+
+/* Interrupt controller */
+#define CPU_S3C2440X_IRQ_BASE (0x4A000000)
+
+/* Clock control */
+#define CPU_S3C2440X_CLKCON_BASE (0x4C000000)
+
+/* LCD */
+#define CPU_S3C2440X_LCD_BASE (0x4D000000)
+
+/* NAND */
+#define CPU_S3C2440X_NAND_BASE (0x4E000000)
+
+/* serial port base */
+#define CPU_S3C2440X_SERIAL_BASE (0x50000000)
+
+/* Timers */
+#define CPU_S3C2440X_TIMERS_BASE (0x51000000)
+
+/* Watchdog */
+#define CPU_S3C2440X_WDOG_BASE (0x53000000)
+
+/* IIC */
+#define CPU_S3C2440X_IIC_BASE (0x54000000)
+
+/* GPIO */
+#define CPU_S3C2440X_GPIO_BASE (0x56000000)
+
+/* Real time clock */
+#define CPU_S3C2440X_RTC_BASE (0x57000000)
+
+/* Initialise a Samsung S3C2440X SOC ARM core and internal peripherals. */
+S3CState *
+s3c2440x_init(int sdram_size)
+{
+    S3CState *s = (S3CState *)qemu_mallocz(sizeof(S3CState));
+
+    /* Prepare the ARM 920T core */
+    s->cpu_env = cpu_init("arm920t");
+
+    /* S3C2440X SDRAM memory is always at the same physical location */
+    cpu_register_physical_memory(CPU_S3C2440X_RAM,
+                                 ram_size,
+                                 qemu_ram_alloc(sdram_size) | IO_MEM_RAM);
+
+    /* Memory controller */
+    s3c24xx_memc_init(s, CPU_S3C2440X_MEMC_BASE);
+
+    /* S3C2440X SRAM */
+    cpu_register_physical_memory(CPU_S3C2440X_SRAM_BASE,
+                                 4096,
+                                 qemu_ram_alloc(4096) | IO_MEM_RAM);
+
+    /* Add the interrupt controller */
+    s->irqs = s3c24xx_irq_init(s, CPU_S3C2440X_IRQ_BASE);
+
+    /* clock and power control */
+    s3c24xx_clkcon_init(s, CPU_S3C2440X_CLKCON_BASE);
+
+    /* PWM control used for timers */
+    s3c24xx_timers_init(s, CPU_S3C2440X_TIMERS_BASE);
+
+    /* And some GPIO */
+    s3c24xx_gpio_init(s, CPU_S3C2440X_GPIO_BASE, CPU_S3C2440X_IDENT_S3C2440A);
+
+    /* Serial ports */
+    s3c24xx_serial_init(s, 0, CPU_S3C2440X_SERIAL_BASE);
+    s3c24xx_serial_init(s, 1, CPU_S3C2440X_SERIAL_BASE);
+    s3c24xx_serial_init(s, 2, CPU_S3C2440X_SERIAL_BASE);
+
+    /* RTC for time */
+    s3c24xx_rtc_init(s, CPU_S3C2440X_RTC_BASE);
+
+    /* And some IIC */
+    s3c24xx_iic_init(s, CPU_S3C2440X_IIC_BASE);
+
+    /* A two port OHCI controller on IRQ 26 */
+    usb_ohci_init_pxa(CPU_S3C2440X_OHCI, 2, -1, s->irqs[26]);
+
+    /* LCD controller */
+    s->lcd = s3c24xx_lcd_init(CPU_S3C2440X_LCD_BASE, s->irqs[16]);
+
+    /* NAND controller */
+    s3c24xx_nand_init(s, CPU_S3C2440X_NAND_BASE);
+    return s;
+}
diff --git a/hw/s3c2440x.h b/hw/s3c2440x.h
new file mode 100644
index 0000000..86191aa
--- /dev/null
+++ b/hw/s3c2440x.h
@@ -0,0 +1,30 @@
+/* hw/s3c2440x.h
+ *
+ * Samsung s3c2440x cpu register definitions
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#ifndef S3C2440X_H
+#define S3C2440X_H 1
+
+#include "s3c24xx.h"
+
+/* S3C2440 Physical memory areas */
+
+/* Chip select 0 */
+#define CPU_S3C2440X_CS0 (0x00000000)
+#define CPU_S3C2440X_CS1 (0x08000000)
+#define CPU_S3C2440X_CS2 (0x10000000)
+#define CPU_S3C2440X_CS3 (0x18000000)
+#define CPU_S3C2440X_CS4 (0x20000000)
+#define CPU_S3C2440X_CS5 (0x28000000)
+#define CPU_S3C2440X_RAM (0x30000000)
+
+/* s3c2440 SOC initialisation */
+S3CState *s3c2440x_init(int sdram_size);
+
+#endif /* S3C2440X_H */
-- 
1.5.4.3





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