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[Qemu-devel] [PATCH 12/15] Peripheral driver for S3C SOC NAND controller


From: Vincent Sanders
Subject: [Qemu-devel] [PATCH 12/15] Peripheral driver for S3C SOC NAND controller
Date: Wed, 6 May 2009 09:44:51 +0100

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target   |    2 +-
 hw/s3c24xx_nand.c |  136 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 137 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_nand.c

diff --git a/Makefile.target b/Makefile.target
index b5dae70..67226cc 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -676,7 +676,7 @@ OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
 OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
 OBJS+= s3c24xx_serial.o s3c24xx_rtc.o s3c24xx_gpio.o s3c24xx_iic.o
-OBJS+= s3c24xx_lcd.o
+OBJS+= s3c24xx_lcd.o s3c24xx_nand.o
 OBJS+= framebuffer.o
 CPPFLAGS += -DHAS_AUDIO
 endif
diff --git a/hw/s3c24xx_nand.c b/hw/s3c24xx_nand.c
new file mode 100644
index 0000000..e4a8a9e
--- /dev/null
+++ b/hw/s3c24xx_nand.c
@@ -0,0 +1,136 @@
+/* hw/s3c24xx_nand.c
+ *
+ * Samsung S3C24XX NAND emulation
+ *
+ * Copyright 2006, 2008 Ben Dooks, Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+#include "flash.h"
+
+#include "s3c24xx.h"
+
+#define NFCONF 0
+#define NFCMD 1
+#define NFADDR 2
+#define NFDATA 3
+#define NFSTAT 4
+#define NFECC 5
+
+#define NFCE ((soc->nand_reg[NFCONF] & 1<<11) != 0)
+
+static void
+s3c24xx_nand_write_f(void *opaque, target_phys_addr_t addr,
+                     uint32_t value)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int reg = (addr & 0x1f) >> 2;
+
+    if ((reg != NFCONF) && ((soc->nand_reg[NFCONF] & 1<<15) == 0)) {
+        return; /* Ignore the write, the nand is not enabled */
+    }
+
+    switch (reg) {
+    case NFCONF:
+        soc->nand_reg[reg] = value;
+        if (soc->nand_chip != NULL)
+            nand_setpins(soc->nand_chip, 0, 0, NFCE, 1, 0);
+        break;
+
+    case NFCMD:
+        soc->nand_reg[reg] = value;
+        if (soc->nand_chip != NULL) {
+            nand_setpins(soc->nand_chip, 1, 0, NFCE, 1, 0);
+            nand_setio(soc->nand_chip, value);
+        }
+        break;
+
+    case NFADDR:
+        soc->nand_reg[reg] = value;
+        if (soc->nand_chip != NULL) {
+            nand_setpins(soc->nand_chip, 0, 1, NFCE, 1, 0);
+            nand_setio(soc->nand_chip, value);
+        }
+        break;
+
+    case NFDATA:
+        soc->nand_reg[reg] = value;
+        if (soc->nand_chip != NULL) {
+            nand_setpins(soc->nand_chip, 0, 0, NFCE, 1, 0);
+            nand_setio(soc->nand_chip, value);
+        }
+        break;
+
+    default:
+        /* Do nothing because the other registers are read only */
+        break;
+    }
+}
+
+static uint32_t
+s3c24xx_nand_read_f(void *opaque, target_phys_addr_t addr)
+{
+    S3CState *soc = (S3CState *)opaque;
+    int reg = (addr & 0x1f) >> 2;
+    uint32_t ret = soc->nand_reg[reg];
+
+    switch (reg) {
+    case NFDATA:
+        if (soc->nand_chip != NULL) {
+            nand_setpins(soc->nand_chip, 0, 0, NFCE, 1, 0);
+            ret = soc->nand_reg[reg] = nand_getio(soc->nand_chip);
+        } else {
+            ret = soc->nand_reg[ret] = 0;
+        }
+        break;
+
+    case NFSTAT:
+        if (soc->nand_chip != NULL) {
+            nand_getpins(soc->nand_chip, (int *)&ret);
+            soc->nand_reg[reg] = ret;
+        } else {
+            ret = soc->nand_reg[ret] = 0;
+        }
+
+    default:
+        /* The rest read-back what was written to them */
+        break;
+    }
+
+    return ret;
+}
+
+static CPUReadMemoryFunc *s3c24xx_nand_read[] = {
+    &s3c24xx_nand_read_f,
+    &s3c24xx_nand_read_f,
+    &s3c24xx_nand_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_nand_write[] = {
+    &s3c24xx_nand_write_f,
+    &s3c24xx_nand_write_f,
+    &s3c24xx_nand_write_f,
+};
+
+void
+s3c24xx_nand_init(S3CState *soc, target_phys_addr_t base_addr)
+{
+    int tag = cpu_register_io_memory(0, s3c24xx_nand_read, s3c24xx_nand_write, 
soc);
+    cpu_register_physical_memory(base_addr, 0x40, tag);
+
+    memset(soc->nand_reg, 0, sizeof(uint32_t) * 5);
+}
+
+void
+s3c24xx_nand_attach(S3CState *soc, struct nand_flash_s *nand_chip)
+{
+    if (soc->nand_chip != NULL) {
+        /* Detach current nand device */
+        /* no cmd, no addr, not enabled, write protected, no 'gnd' */
+        nand_setpins(soc->nand_chip, 0, 0, 1, 0, 0);
+    }
+    soc->nand_chip = nand_chip;
+}
-- 
1.5.4.3





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