[Qemu-devel] [PATCH 08/16] Peripheral driver for S3C SOC real time clock.

[Vincent Sanders]

Signed-off-by: Vincent Sanders <address@hidden>
---
 Makefile.target  |    2 +-
 hw/s3c2410x.c    |    6 ++
 hw/s3c2440.c     |    6 ++
 hw/s3c24xx.h     |    7 +++
 hw/s3c24xx_rtc.c |  135 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 155 insertions(+), 1 deletions(-)
 create mode 100644 hw/s3c24xx_rtc.c

diff --git a/Makefile.target b/Makefile.target
index 2888e86..2596943 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -649,7 +649,7 @@ OBJS+= nseries.o blizzard.o onenand.o vga.o cbus.o 
tusb6010.o usb-musb.o
 OBJS+= mst_fpga.o mainstone.o
 OBJS+= musicpal.o pflash_cfi02.o
 OBJS+= s3c24xx_memc.o s3c24xx_irq.o s3c24xx_clkcon.o s3c24xx_timers.o
-OBJS+= s3c24xx_serial.o
+OBJS+= s3c24xx_serial.o s3c24xx_rtc.o
 OBJS+= s3c2410x.o s3c2440.o
 OBJS+= framebuffer.o
 OBJS+= syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
diff --git a/hw/s3c2410x.c b/hw/s3c2410x.c
index 084f9ec..21ecec2 100644
--- a/hw/s3c2410x.c
+++ b/hw/s3c2410x.c
@@ -36,6 +36,9 @@
 /* Timer controller */
 #define CPU_S3C2410X_TIMERS_BASE (CPU_S3C2410X_PERIPHERAL + 0x11000000)
 
+/* Real time clock */
+#define CPU_S3C2410X_RTC_BASE (CPU_S3C2410X_PERIPHERAL + 0x17000000)
+
 /* Initialise a Samsung S3C2410X SOC ARM core and internal peripherals. */
 S3CState *
 s3c2410x_init(int sdram_size)
@@ -74,5 +77,8 @@ s3c2410x_init(int sdram_size)
     s->uart[1] = s3c24xx_serial_init(s, serial_hds[1], 
CPU_S3C2410X_SERIAL1_BASE, 35);
     s->uart[2] = s3c24xx_serial_init(s, serial_hds[2], 
CPU_S3C2410X_SERIAL2_BASE, 38);
 
+    /* Real time clcok */
+    s->rtc = s3c24xx_rtc_init(CPU_S3C2410X_RTC_BASE);
+
     return s;
 }
diff --git a/hw/s3c2440.c b/hw/s3c2440.c
index 3896965..91f4341 100644
--- a/hw/s3c2440.c
+++ b/hw/s3c2440.c
@@ -36,6 +36,9 @@
 /* Timer controller */
 #define CPU_S3C2440_TIMERS_BASE (CPU_S3C2440_PERIPHERAL + 0x11000000)
 
+/* Real time clock */
+#define CPU_S3C2440_RTC_BASE (CPU_S3C2440_PERIPHERAL + 0x17000000)
+
 /* Initialise a Samsung S3C2440 SOC ARM core and internal peripherals. */
 S3CState *
 s3c2440_init(int sdram_size)
@@ -72,5 +75,8 @@ s3c2440_init(int sdram_size)
     s->uart[1] = s3c24xx_serial_init(s, serial_hds[1], 
CPU_S3C2440_SERIAL1_BASE, 35);
     s->uart[2] = s3c24xx_serial_init(s, serial_hds[2], 
CPU_S3C2440_SERIAL2_BASE, 38);
 
+    /* Real time clcok */
+    s->rtc = s3c24xx_rtc_init(CPU_S3C2440_RTC_BASE);
+
     return s;
 }
diff --git a/hw/s3c24xx.h b/hw/s3c24xx.h
index 5a2e806..643d841 100644
--- a/hw/s3c24xx.h
+++ b/hw/s3c24xx.h
@@ -30,6 +30,9 @@ typedef struct S3CState_s {
     /* Serial ports */
     struct s3c24xx_serial_dev_s *uart[3];
 
+    /* Real time clock */
+    struct s3c24xx_rtc_state_s *rtc;
+
 } S3CState;
 
 
@@ -51,4 +54,8 @@ struct s3c24xx_timers_state_s *s3c24xx_timers_init(S3CState 
*soc, target_phys_ad
 /* initialise a serial port controller */
 struct s3c24xx_serial_dev_s *s3c24xx_serial_init(S3CState *soc, 
CharDriverState *chr, target_phys_addr_t base_addr, int irqn);
 
+/* Initialise real time clock */
+struct s3c24xx_rtc_state_s *s3c24xx_rtc_init(target_phys_addr_t base_addr);
+
+
 #endif /* S3C24XX_H */
diff --git a/hw/s3c24xx_rtc.c b/hw/s3c24xx_rtc.c
new file mode 100644
index 0000000..2a2124f
--- /dev/null
+++ b/hw/s3c24xx_rtc.c
@@ -0,0 +1,135 @@
+/* hw/s3c24xx_rtc.c
+ *
+ * Samsung S3C24XX RTC emulation
+ *
+ * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2
+ */
+
+#include "hw.h"
+
+#include "s3c24xx.h"
+
+
+/* RTC Control RW Byte */
+#define S3C_REG_RTCCON 0
+/* Tick time count RW Byte */
+#define S3C_REG_TICNT 1
+/* RTC Alarm Control RW Byte */
+#define S3C_REG_RTCALM 4
+/* Alarm second */
+#define S3C_REG_ALMSEC 5
+/* Alarm minute */
+#define S3C_REG_ALMMIN 6
+/* Alarm hour */
+#define S3C_REG_ALMHOUR 7
+/* Alarm day */
+#define S3C_REG_ALMDATE 8
+/* Alarm month */
+#define S3C_REG_ALMMON 9
+/* Alarm year */
+#define S3C_REG_ALMYEAR 10
+/* RTC Round Reset */
+#define S3C_REG_RTCRST 11
+/* BCD Second */
+#define S3C_REG_BCDSEC 12
+/* BCD Minute */
+#define S3C_REG_BCDMIN 13
+/* BCD Hour */
+#define S3C_REG_BCDHOUR 14
+/* BCD Day */
+#define S3C_REG_BCDDATE 15
+/* BCD Day of week */
+#define S3C_REG_BCDDAY 16
+/* BCD Month */
+#define S3C_REG_BCDMON 17
+/* BCD Year */
+#define S3C_REG_BCDYEAR 18
+
+/* Real Time clock state */
+struct s3c24xx_rtc_state_s {
+    uint32_t rtc_reg[19];
+};
+
+
+static inline int to_bcd(int a)
+{
+    return ((a/10)<<4) | (a%10);
+}
+
+static void update_time(struct s3c24xx_rtc_state_s *s)
+{
+    time_t ti;
+    struct tm *tm;
+    /* update the RTC registers from system time */
+    time(&ti);
+    tm = gmtime(&ti);
+    s->rtc_reg[S3C_REG_BCDSEC] = to_bcd(tm->tm_sec);
+    s->rtc_reg[S3C_REG_BCDMIN] = to_bcd(tm->tm_min);
+    s->rtc_reg[S3C_REG_BCDHOUR] = to_bcd(tm->tm_hour);
+    s->rtc_reg[S3C_REG_BCDDATE] = to_bcd(tm->tm_mday);
+    s->rtc_reg[S3C_REG_BCDDAY] = to_bcd(tm->tm_wday + 1);
+    s->rtc_reg[S3C_REG_BCDMON] = to_bcd(tm->tm_mon + 1);
+    s->rtc_reg[S3C_REG_BCDYEAR] =  to_bcd(tm->tm_year - 100);
+}
+
+static void
+s3c24xx_rtc_write_f(void *opaque, target_phys_addr_t addr_, uint32_t value)
+{
+    struct s3c24xx_rtc_state_s *s = (struct s3c24xx_rtc_state_s *)opaque;
+    int addr = (addr_ - 0x40) >> 2;
+    if (addr < 0 || addr > 18)
+        addr = 18;
+
+    s->rtc_reg[addr] = value;
+}
+
+static uint32_t
+s3c24xx_rtc_read_f(void *opaque, target_phys_addr_t addr_)
+{
+    struct s3c24xx_rtc_state_s *s = (struct s3c24xx_rtc_state_s *)opaque;
+    int addr = (addr_ - 0x40) >> 2;
+
+    if (addr < 0 || addr > 18)
+        addr = 18;
+
+    update_time(s);
+
+    return s->rtc_reg[addr];
+}
+
+static CPUReadMemoryFunc *s3c24xx_rtc_read[] = {
+    &s3c24xx_rtc_read_f,
+    &s3c24xx_rtc_read_f,
+    &s3c24xx_rtc_read_f,
+};
+
+static CPUWriteMemoryFunc *s3c24xx_rtc_write[] = {
+    &s3c24xx_rtc_write_f,
+    &s3c24xx_rtc_write_f,
+    &s3c24xx_rtc_write_f,
+};
+
+
+struct s3c24xx_rtc_state_s *
+s3c24xx_rtc_init(target_phys_addr_t base_addr)
+{
+    int tag;
+    struct s3c24xx_rtc_state_s *s;
+
+    s = qemu_mallocz(sizeof(struct s3c24xx_rtc_state_s));
+
+    tag = cpu_register_io_memory(0, s3c24xx_rtc_read, s3c24xx_rtc_write, s);
+
+    /* there are only 19 real registers but they start at offset 0x40 into the
+     * range so we have 35 registers mapped
+     */
+    cpu_register_physical_memory(base_addr, 35 * 4, tag);
+
+    /* set the RTC so it appears active */
+    s->rtc_reg[S3C_REG_RTCCON] = 1;
+
+    return s;
+}
-- 
1.6.0.4