[Qemu-devel] [PATCH 1/3] m68k: allow fpu to manage double single data type.

[Laurent Vivier]

This patch allows to manage instructions like "fcmpd #2.2, %fp0".
Original function manages only data accessed through an address register.

Signed-off-by: Laurent Vivier <address@hidden>
---
 target-m68k/translate.c |   71 +++++++++++++++++++++++++----------------------
 1 files changed, 38 insertions(+), 33 deletions(-)

diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index ea6b34b..223b296 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3115,40 +3115,45 @@ DISAS_INSN(fpu)
             goto undef;
         }
         if (opsize == OS_DOUBLE) {
-            tmp32 = tcg_temp_new_i32();
-            tcg_gen_mov_i32(tmp32, AREG(insn, 0));
-            switch ((insn >> 3) & 7) {
-            case 2:
-            case 3:
-                break;
-            case 4:
-                tcg_gen_addi_i32(tmp32, tmp32, -8);
-                break;
-            case 5:
-                offset = ldsw_code(s->pc);
-                s->pc += 2;
-                tcg_gen_addi_i32(tmp32, tmp32, offset);
-                break;
-            case 7:
-                offset = ldsw_code(s->pc);
-                offset += s->pc - 2;
-                s->pc += 2;
-                tcg_gen_addi_i32(tmp32, tmp32, offset);
-                break;
-            default:
-                goto undef;
-            }
-            src = gen_load64(s, tmp32);
-            switch ((insn >> 3) & 7) {
-            case 3:
-                tcg_gen_addi_i32(tmp32, tmp32, 8);
-                tcg_gen_mov_i32(AREG(insn, 0), tmp32);
-                break;
-            case 4:
-                tcg_gen_mov_i32(AREG(insn, 0), tmp32);
-                break;
+            if ((insn & 7) == 4) {
+                src = gen_load64(s, tcg_const_i32(s->pc));
+                s->pc += 8;
+            } else {
+                tmp32 = tcg_temp_new_i32();
+                tcg_gen_mov_i32(tmp32, AREG(insn, 0));
+                switch ((insn >> 3) & 7) {
+                case 2:
+                case 3:
+                    break;
+                case 4:
+                    tcg_gen_addi_i32(tmp32, tmp32, -8);
+                    break;
+                case 5:
+                    offset = ldsw_code(s->pc);
+                    s->pc += 2;
+                    tcg_gen_addi_i32(tmp32, tmp32, offset);
+                    break;
+                case 7:
+                    offset = ldsw_code(s->pc);
+                    offset += s->pc - 2;
+                    s->pc += 2;
+                    tcg_gen_addi_i32(tmp32, tmp32, offset);
+                    break;
+                default:
+                    goto undef;
+                }
+                src = gen_load64(s, tmp32);
+                switch ((insn >> 3) & 7) {
+                case 3:
+                    tcg_gen_addi_i32(tmp32, tmp32, 8);
+                    tcg_gen_mov_i32(AREG(insn, 0), tmp32);
+                    break;
+                case 4:
+                    tcg_gen_mov_i32(AREG(insn, 0), tmp32);
+                    break;
+                }
+                tcg_temp_free_i32(tmp32);
             }
-            tcg_temp_free_i32(tmp32);
         } else {
             SRC_EA(tmp32, opsize, 1, NULL);
             src = tcg_temp_new_i64();
-- 
1.5.6.5