[Qemu-devel] [PATCH 04/14] AT91 Power Management Unit

[Filip Navara]

The isolated behavior of PMU is emulated completely, but the effects on other
parts of the system are not. Since QEMU lacks any API for proper modeling of
the system and peripheral clocks, the actual enabling and disabling of clocks
has no effect on the emulated system.

The master clock frequency is exposed using a global variable for use by other
system components, such as timers.

Signed-off-by: Filip Navara <address@hidden>
---
 Makefile.target |    2 +-
 hw/at91.h       |   32 +++++++
 hw/at91_pmc.c   |  280 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 313 insertions(+), 1 deletions(-)
 create mode 100644 hw/at91.h
 create mode 100644 hw/at91_pmc.c

diff --git a/Makefile.target b/Makefile.target
index 4a81e68..ecaba36 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -666,7 +666,7 @@ obj-y += framebuffer.o
 obj-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
 obj-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
 obj-y += syborg_virtio.o
-obj-y += at91_aic.o
+obj-y += at91_aic.o at91_pmc.o
 obj-y += gpio_rotary.o gpio_keypad.o
 CPPFLAGS += -DHAS_AUDIO
 endif
diff --git a/hw/at91.h b/hw/at91.h
new file mode 100644
index 0000000..9b0c937
--- /dev/null
+++ b/hw/at91.h
@@ -0,0 +1,32 @@
+/*
+ * AT91 Miscellaneous Definitions
+ *
+ * Copyright (c) 2009 Filip Navara
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef AT91_H
+#define AT91_H 1
+
+/* Frequency of the master clock as programmed by the Power Management
+   Controller. */
+extern int at91_master_clock_frequency;
+
+#endif /* !AT91_H */
diff --git a/hw/at91_pmc.c b/hw/at91_pmc.c
new file mode 100644
index 0000000..78c6c99
--- /dev/null
+++ b/hw/at91_pmc.c
@@ -0,0 +1,280 @@
+/*
+ * AT91 Power Management Controller
+ *
+ * Copyright (c) 2009 Filip Navara
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "qemu-timer.h"
+#include "at91.h"
+
+#define PMC_SIZE        0x70
+
+#define PMC_SCER        0x00 /* System Clock Enable Register */
+#define PMC_SCDR        0x04 /* System Clock Disable Register */
+#define PMC_SCSR        0x08 /* System Clock Status Register */
+#define PMC_PCER        0x10 /* Peripheral Clock Enable Register */
+#define PMC_PCDR        0x14 /* Peripheral Clock Disable Register */
+#define PMC_PCSR        0x18 /* Peripheral Clock Status Register */
+#define PMC_MOR         0x20 /* Main Oscillator Register */
+#define PMC_MCFR        0x24 /* Main Clock Frequency Register */
+#define PMC_PLLA        0x28 /* PLL A Register */
+#define PMC_PLLB        0x2c /* PLL B Register */
+#define PMC_MCKR        0x30 /* Master Clock Register */
+#define PMC_PCKR        0x40 /* Programmable Clock Register */
+#define PMC_IER         0x60 /* Interrupt Enable Register */
+#define PMC_IDR         0x64 /* Interrupt Disable Register */
+#define PMC_IMR         0x6c /* Interrupt Mask Register */
+#define PMC_SR          0x68 /* Status Register */
+
+#define SR_MOSCS        0x01
+#define SR_LOCKA        0x02
+#define SR_LOCKB        0x04
+#define SR_MCKRDY       0x08
+#define SR_PCK0RDY      0x100
+#define SR_PCK1RDY      0x200
+#define SR_PCK2RDY      0x400
+#define SR_PCK3RDY      0x800
+
+#define SO_FREQ         32768
+#define MO_FREQ         9216000
+
+int at91_master_clock_frequency = SO_FREQ;
+
+typedef struct PMCState {
+    SysBusDevice busdev;
+    qemu_irq parent_irq;
+    uint32_t scsr;
+    uint32_t pcsr;
+    uint32_t mor;
+    uint32_t plla;
+    uint32_t pllb;
+    uint32_t mckr;
+    uint32_t pckr[4];
+    uint32_t sr;
+    uint32_t imr;
+    uint32_t mck_freq;
+} PMCState;
+
+static void at91_pmc_update_irq(PMCState *s)
+{
+    qemu_set_irq(s->parent_irq, !!(s->sr & s->imr));
+}
+
+static void at91_update_master_clock(PMCState *s)
+{
+    int mck_freq = MO_FREQ;
+
+    /* Clock selection */
+    switch (s->mckr & 3) {
+    case 0: /* Slow */
+        mck_freq = SO_FREQ;
+        break;
+    case 1: /* Main */
+        if (!(s->sr & SR_MOSCS))
+            mck_freq = 0;
+        break;
+    case 2: /* PLL A */
+        if ((s->plla & 0xff) != 0 &&
+            (s->plla & 0x3ff80) != 0) {
+            mck_freq /= s->plla & 0xff;
+            mck_freq *= ((s->plla >> 16) & 0x7ff) + 1;
+        } else {
+            mck_freq = 0;
+        }
+        break;
+    case 3: /* PLL B */
+        if ((s->pllb & 0xff) != 0 &&
+            (s->pllb & 0x3ff80) != 0) {
+            mck_freq /= s->pllb & 0xff;
+            mck_freq *= ((s->pllb >> 16) & 0x7ff) + 1;
+        } else {
+            mck_freq = 0;
+        }
+        break;
+    }
+
+    if (mck_freq != 0) {
+        mck_freq /= 1 << ((s->mckr >> 2) & 7);
+        mck_freq /= 1 << ((s->mckr >> 8) & 3);
+        s->mck_freq = mck_freq;
+        at91_master_clock_frequency = mck_freq;
+        s->sr |= SR_MCKRDY;
+    } else {
+        s->sr &= ~SR_MCKRDY;
+    }
+}
+
+static uint32_t at91_pmc_mem_read(void *opaque, target_phys_addr_t offset)
+{
+    PMCState *s = opaque;
+
+    switch (offset) {
+    case PMC_SCSR:
+        return s->scsr;
+    case PMC_PCSR:
+        return s->pcsr;
+    case PMC_MOR:
+        return s->mor;
+    case PMC_MCFR:
+        if (s->mor & 1)
+            return (1 << 16) | (MO_FREQ / SO_FREQ / 16);
+        return 0;
+    case PMC_PCKR ... PMC_PCKR + 15:
+        return s->pckr[(offset - PMC_PCKR) >> 2];
+    case PMC_SR:
+        return s->sr;
+    case PMC_IMR:
+        return s->imr;
+    default:
+        return 0;
+    }
+}
+
+static void at91_pmc_mem_write(void *opaque, target_phys_addr_t offset,
+                uint32_t value)
+{
+    PMCState *s = opaque;
+
+    switch (offset) {
+    case PMC_SCER:
+        s->scsr |= value & 0xf80;
+        break;
+    case PMC_SCDR:
+        s->scsr &= ~(value & 0xf80);
+        break;
+    case PMC_PCER:
+        s->pcsr |= value & ~3;
+        break;
+    case PMC_PCDR:
+        s->pcsr &= ~(value & ~3);
+        break;
+    case PMC_MOR:
+        /* Main Oscillator bypassing is not supported, so first two
+           bits are ignored. Bits 8-15 specify the OSCOUNT, which is
+           also currently ignored. */ 
+        s->mor = value;
+        s->sr |= SR_MOSCS;
+        break;
+    case PMC_PLLA:
+        s->plla = value;
+        /* OUTA, PLLACOUNT ignored for now */
+        s->sr |= SR_LOCKA;
+        break;
+    case PMC_PLLB:
+        s->pllb = value;
+        /* OUTB, PLLBCOUNT ignored for now */
+        s->sr |= SR_LOCKB;
+        break;
+    case PMC_MCKR:
+        s->mckr = value;
+        break;
+    case PMC_PCKR ... PMC_PCKR + 15:
+        s->pckr[(offset - PMC_PCKR) >> 2] = value;
+        break;
+    case PMC_IER:
+        s->imr |= value;
+        break;
+    case PMC_IDR:
+        s->imr &= ~value;
+        break;
+    default:
+        return;
+    }
+
+    at91_update_master_clock(s);
+    at91_pmc_update_irq(s);
+}
+
+static CPUReadMemoryFunc *at91_pmc_readfn[] = {
+    at91_pmc_mem_read,
+    at91_pmc_mem_read,
+    at91_pmc_mem_read,
+};
+
+static CPUWriteMemoryFunc *at91_pmc_writefn[] = {
+    at91_pmc_mem_write,
+    at91_pmc_mem_write,
+    at91_pmc_mem_write,
+};
+
+static void at91_pmc_save(QEMUFile *f, void *opaque)
+{
+    PMCState *s = opaque;
+    int i;
+
+    qemu_put_be32(f, s->scsr);
+    qemu_put_be32(f, s->pcsr);
+    qemu_put_be32(f, s->mor);
+    qemu_put_be32(f, s->plla);
+    qemu_put_be32(f, s->pllb);
+    qemu_put_be32(f, s->mckr);
+    for (i = 0; i < 4; i++) {
+        qemu_put_be32(f, s->pckr[i]);
+    }
+    qemu_put_be32(f, s->sr);
+    qemu_put_be32(f, s->imr);
+}
+
+static int at91_pmc_load(QEMUFile *f, void *opaque, int version_id)
+{
+    PMCState *s = opaque;
+    int i;
+
+    if (version_id != 1)
+        return -EINVAL;
+
+    s->scsr = qemu_get_be32(f);
+    s->pcsr = qemu_get_be32(f);
+    s->mor = qemu_get_be32(f);
+    s->plla = qemu_get_be32(f);
+    s->pllb = qemu_get_be32(f);
+    s->mckr = qemu_get_be32(f);
+    for (i = 0; i < 4; i++) {
+        s->pckr[i] = qemu_get_be32(f);
+    }
+    s->sr = qemu_get_be32(f);
+    s->imr = qemu_get_be32(f);
+
+    at91_update_master_clock(s);
+
+    return 0;
+}
+
+static void at91_pmc_init(SysBusDevice *dev)
+{
+    PMCState *s = FROM_SYSBUS(typeof (*s), dev);
+    int pmc_regs;
+
+    sysbus_init_irq(dev, &s->parent_irq);
+
+    pmc_regs = cpu_register_io_memory(at91_pmc_readfn, at91_pmc_writefn, s);
+    sysbus_init_mmio(dev, PMC_SIZE, pmc_regs);
+
+    register_savevm("at91_pmc", -1, 1, at91_pmc_save, at91_pmc_load, s);
+}
+
+static void at91_pmc_register(void)
+{
+    sysbus_register_dev("at91,pmc", sizeof(PMCState), at91_pmc_init);
+}
+
+device_init(at91_pmc_register)
-- 
1.6.3.msysgit.0