After comments from address@hidden and address@hidden, here's the
2nd try:
The sequence of reading from eeprom is "offset by one" moved because
of a false detection
of a clock cycle after an eeprom reset. Keeping the last clock value
after a reset keeps it in sync.
Signed-off-by: Naphtali Sprei <address@hidden>
---
hw/e1000.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/e1000.c b/hw/e1000.c
index 4ac8918..15598ab 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -262,6 +262,8 @@ set_eecd(E1000State *s, int index, uint32_t val)
}
if (!(val & E1000_EECD_CS)) { // rising, no CS
(EEPROM reset)
memset(&s->eecd_state, 0, sizeof s->eecd_state);
+ // restore old_eecd's E1000_EECD_SK to avoid false detection
of a clock edge