[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH] target-mips: fix conditional moves off fp condition
From: |
Nathan Froyd |
Subject: |
[Qemu-devel] [PATCH] target-mips: fix conditional moves off fp condition codes |
Date: |
Tue, 25 Aug 2009 08:20:00 -0700 |
Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code. However,
get_fp_bit returns the bit number of the condition code, not a
bitmask. (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)
Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).
Signed-off-by: Nathan Froyd <address@hidden>
---
target-mips/translate.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6a1273f..a2b2edb 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5896,7 +5896,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs,
int cc, int tf)
l1 = gen_new_label();
t0 = tcg_temp_new_i32();
- tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
+ tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_temp_free_i32(t0);
if (rs == 0) {
@@ -5918,7 +5918,7 @@ static inline void gen_movcf_s (int fs, int fd, int cc,
int tf)
else
cond = TCG_COND_NE;
- tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
+ tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
gen_load_fpr32(t0, fs);
gen_store_fpr32(t0, fd);
@@ -5938,7 +5938,7 @@ static inline void gen_movcf_d (DisasContext *ctx, int
fs, int fd, int cc, int t
else
cond = TCG_COND_NE;
- tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
+ tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
tcg_temp_free_i32(t0);
fp0 = tcg_temp_new_i64();
@@ -5960,13 +5960,13 @@ static inline void gen_movcf_ps (int fs, int fd, int
cc, int tf)
else
cond = TCG_COND_NE;
- tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
+ tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
tcg_gen_brcondi_i32(cond, t0, 0, l1);
gen_load_fpr32(t0, fs);
gen_store_fpr32(t0, fd);
gen_set_label(l1);
- tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1));
+ tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1));
tcg_gen_brcondi_i32(cond, t0, 0, l2);
gen_load_fpr32h(t0, fs);
gen_store_fpr32h(t0, fd);
--
1.6.3.2
- [Qemu-devel] [PATCH] target-mips: fix conditional moves off fp condition codes,
Nathan Froyd <=