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Re: [Qemu-devel] [PATCH] ARM back-end: Fix register numbering for div/d
From: |
Laurent Desnogues |
Subject: |
Re: [Qemu-devel] [PATCH] ARM back-end: Fix register numbering for div/divu and add TCG not |
Date: |
Fri, 25 Sep 2009 17:46:29 +0200 |
On Sat, Aug 22, 2009 at 2:03 PM, andrzej zaborowski <address@hidden> wrote:
> 2009/7/24 Laurent Desnogues <address@hidden>:
>> Hello,
>>
>> this patch:
>>
>> - fixes argument numbers for div2 and divu2
>
> But "0" is not defined in target_parse_constraint? Does div2 not work
> as is now?
Given Gary Thomas latest question, I guess it's time to
resurrect that discussion :-)
Constraints defined as numbers are handled internally
by TCG in tcg_add_target_add_op_defs. My understanding
is that they mean that an input and an output arg are aliased.
I don't think it's what the constraint for div2 and divu2 is
trying to express.
Also the div helper looks broken: it potentially restores less
registers than what it saved, and uses ldrt.
My proposed fix was completely wrong, but I have no time
to make a correct one.
Laurent
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Laurent Desnogues <=