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Re: [Qemu-devel] [PATCH 1/3] tcg: add ext{8,16,32}u_i{32,64} TCG ops
From: |
Nathan Froyd |
Subject: |
Re: [Qemu-devel] [PATCH 1/3] tcg: add ext{8,16,32}u_i{32,64} TCG ops |
Date: |
Fri, 2 Oct 2009 13:07:12 -0700 |
User-agent: |
Mutt/1.5.13 (2006-08-11) |
On Wed, Sep 30, 2009 at 11:09:35PM +0200, Aurelien Jarno wrote:
> Currently zero extensions ops are implemented by a and op with a
> constant. This is then catched in some backend, and replaced by
> a zero extension instruction. While this works well on RISC
> machines, this adds a useless register move on non-RISC machines.
>
> This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be
> implemented in the backends to avoid emitting useless register
> moves.
I have to ask--does this make things go faster?
-Nathan
- [Qemu-devel] [PATCH 1/3] tcg: add ext{8,16,32}u_i{32,64} TCG ops, Aurelien Jarno, 2009/10/02
- [Qemu-devel] [PATCH 3/3] tcg/i386: add support for ext{8, 16, 32}u_i{32, 64} TCG ops, Aurelien Jarno, 2009/10/02
- [Qemu-devel] [PATCH 2/3] tcg/x86_64: add support for ext{8, 16, 32}u_i{32, 64} TCG ops, Aurelien Jarno, 2009/10/02
- Re: [Qemu-devel] [PATCH 1/3] tcg: add ext{8,16,32}u_i{32,64} TCG ops,
Nathan Froyd <=