Re: [Qemu-devel] [PATCH 1/3] tcg: add ext{8,16,32}u_i{32,64} TCG ops

[Aurelien Jarno]

On Fri, Oct 02, 2009 at 01:07:12PM -0700, Nathan Froyd wrote:
> On Wed, Sep 30, 2009 at 11:09:35PM +0200, Aurelien Jarno wrote:
> > Currently zero extensions ops are implemented by a and op with a
> > constant. This is then catched in some backend, and replaced by
> > a zero extension instruction. While this works well on RISC
> > machines, this adds a useless register move on non-RISC machines.
> > 
> > This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be
> > implemented in the backends to avoid emitting useless register
> > moves.
> 
> I have to ask--does this make things go faster?
> 

It depends on the target, it needs to use zero extension (MIPS for
example almost only does sign extension). It gives a 1.5% gain on
my test with qemu-86_64.

It should also give a gain on 64 bit system targets running a 32 
bit OS (i386 on x86_64, ppc on ppc64), as they are doing a zero 
extension on a lot of instruction.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net