Re: [Qemu-devel] [PATCH 13/18] Convert disas_neon_ls_insn not to use cpu_T.

[Aurelien Jarno]

On Sun, Jul 19, 2009 at 03:50:03PM +0000, Filip Navara wrote:
> Signed-off-by: Filip Navara <address@hidden>
> ---
>  target-arm/translate.c |   69 ++++++++++++++++++++++++-----------------------
>  1 files changed, 35 insertions(+), 34 deletions(-)
> 
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index fc40d5e..6a57918 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3767,6 +3767,7 @@ static int disas_neon_ls_insn(CPUState * env, 
> DisasContext *s, uint32_t insn)
>      int load;
>      int shift;
>      int n;
> +    TCGv addr;
>      TCGv tmp;
>      TCGv tmp2;
>  
> @@ -3776,6 +3777,7 @@ static int disas_neon_ls_insn(CPUState * env, 
> DisasContext *s, uint32_t insn)
>      rn = (insn >> 16) & 0xf;
>      rm = insn & 0xf;
>      load = (insn & (1 << 21)) != 0;
> +    addr = new_tmp();
>      if ((insn & (1 << 23)) == 0) {
>          /* Load store all elements.  */
>          op = (insn >> 8) & 0xf;
> @@ -3784,32 +3786,30 @@ static int disas_neon_ls_insn(CPUState * env, 
> DisasContext *s, uint32_t insn)
>              return 1;
>          nregs = neon_ls_element_type[op].nregs;
>          interleave = neon_ls_element_type[op].interleave;
> -        gen_movl_T1_reg(s, rn);
> +        tcg_gen_mov_i32(addr, cpu_R[rn]);
>          stride = (1 << size) * interleave;
>          for (reg = 0; reg < nregs; reg++) {
>              if (interleave > 2 || (interleave == 2 && nregs == 2)) {
> -                gen_movl_T1_reg(s, rn);
> -                gen_op_addl_T1_im((1 << size) * reg);
> +                tcg_gen_add_i32(addr, cpu_R[rn], (1 << size) * reg);

That should be tcg_gen_addi_i32()

>              } else if (interleave == 2 && nregs == 4 && reg == 2) {
> -                gen_movl_T1_reg(s, rn);
> -                gen_op_addl_T1_im(1 << size);
> +                tcg_gen_add_i32(addr, cpu_R[rn], 1 << size);
>              }

That should be tcg_gen_addi_i32()

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net