Re: [Qemu-devel] [PATCH v2 05/10] target-arm: optimize arm load/store multiple ops

[Aurelien Jarno]

On Sat, Oct 24, 2009 at 03:19:04PM +0300, address@hidden wrote:
> From: Juha Riihimäki <address@hidden>
> 
> RM load/store multiple instructions can be slightly optimized by
> loading the register offset constant into a variable outside the
> register loop and using the preloaded variable inside the loop instead
> of reloading the offset value to a temporary variable on each loop
> iteration. This causes less TCG ops to be generated for a ARM load/
> store multiple instruction if there are more than one register
> accessed, otherwise the number of generated TCG ops is the same.
> 
> Signed-off-by: Juha Riihimäki <address@hidden>
> Acked-by: Laurent Desnogues <address@hidden>

This patch breaks, the boot of an arm kernel, as tmp2 is used elsewhere
within this code path.

OTOH, while it reduce the number of TCG ops, that should not impact the
generated host asm code, as most (all ?) targets are able to add a
small constant value to a register in one instruction.

> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 38fb833..d1e2ed2 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env, DisasContext 
> *s)
>                  }
>                  rn = (insn >> 16) & 0xf;
>                  addr = load_reg(s, rn);
> +                tmp2 = tcg_const_i32(4);
>  
>                  /* compute total size */
>                  loaded_base = 0;
> @@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env, DisasContext 
> *s)
>                  if (insn & (1 << 23)) {
>                      if (insn & (1 << 24)) {
>                          /* pre increment */
> -                        tcg_gen_addi_i32(addr, addr, 4);
> +                        tcg_gen_add_i32(addr, addr, tmp2);
>                      } else {
>                          /* post increment */
>                      }
> @@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env, DisasContext 
> *s)
>                          j++;
>                          /* no need to add after the last transfer */
>                          if (j != n)
> -                            tcg_gen_addi_i32(addr, addr, 4);
> +                            tcg_gen_add_i32(addr, addr, tmp2);
>                      }
>                  }
>                  if (insn & (1 << 21)) {
> @@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env, DisasContext 
> *s)
>                              /* pre increment */
>                          } else {
>                              /* post increment */
> -                            tcg_gen_addi_i32(addr, addr, 4);
> +                            tcg_gen_add_i32(addr, addr, tmp2);
>                          }
>                      } else {
>                          if (insn & (1 << 24)) {
> @@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env, DisasContext 
> *s)
>                  } else {
>                      dead_tmp(addr);
>                  }
> +                tcg_temp_free_i32(tmp2);
>                  if (loaded_base) {
>                      store_reg(s, rn, loaded_var);
>                  }
> -- 
> 1.6.5
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net