[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 05/11] target-mips: make gen_compute_branch 16/32-bi
From: |
Nathan Froyd |
Subject: |
[Qemu-devel] [PATCH 05/11] target-mips: make gen_compute_branch 16/32-bit-aware |
Date: |
Mon, 23 Nov 2009 12:50:03 -0800 |
Signed-off-by: Nathan Froyd <address@hidden>
---
target-mips/translate.c | 15 ++++++++-------
1 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c03d1bf..1157e97 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2406,6 +2406,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n,
target_ulong dest)
/* Branches (before delay slot) */
static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
+ int insn_bytes,
int rs, int rt, int32_t offset)
{
target_ulong btgt = -1;
@@ -2434,7 +2435,7 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
gen_load_gpr(t1, rt);
bcond_compute = 1;
}
- btgt = ctx->pc + 4 + offset;
+ btgt = ctx->pc + insn_bytes + offset;
break;
case OPC_BGEZ:
case OPC_BGEZAL:
@@ -2453,12 +2454,12 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
gen_load_gpr(t0, rs);
bcond_compute = 1;
}
- btgt = ctx->pc + 4 + offset;
+ btgt = ctx->pc + insn_bytes + offset;
break;
case OPC_J:
case OPC_JAL:
/* Jump to immediate */
- btgt = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
+ btgt = ((ctx->pc + insn_bytes) & (int32_t)0xF0000000) |
(uint32_t)offset;
break;
case OPC_JR:
case OPC_JALR:
@@ -7670,7 +7671,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
gen_muldiv(ctx, op1, rs, rt);
break;
case OPC_JR ... OPC_JALR:
- gen_compute_branch(ctx, op1, rs, rd, sa);
+ gen_compute_branch(ctx, op1, 4, rs, rd, sa);
return;
case OPC_TGE ... OPC_TEQ: /* Traps */
case OPC_TNE:
@@ -7959,7 +7960,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
switch (op1) {
case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
case OPC_BLTZAL ... OPC_BGEZALL:
- gen_compute_branch(ctx, op1, rs, -1, imm << 2);
+ gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
return;
case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
case OPC_TNEI:
@@ -8078,11 +8079,11 @@ static void decode_opc (CPUState *env, DisasContext
*ctx)
break;
case OPC_J ... OPC_JAL: /* Jump */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
- gen_compute_branch(ctx, op, rs, rt, offset);
+ gen_compute_branch(ctx, op, 4, rs, rt, offset);
return;
case OPC_BEQ ... OPC_BGTZ: /* Branch */
case OPC_BEQL ... OPC_BGTZL:
- gen_compute_branch(ctx, op, rs, rt, imm << 2);
+ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
return;
case OPC_LB ... OPC_LWR: /* Load and stores */
case OPC_SB ... OPC_SW:
--
1.6.3.2
- Re: [Qemu-devel] [PATCH 03/11] target-mips: change interrupt bits to be mips16-aware, (continued)
- [Qemu-devel] [PATCH 07/11] target-mips: split out delay slot handling, Nathan Froyd, 2009/11/23
- [Qemu-devel] [PATCH 01/11] target-mips: add ISAMode bits for mips16 execution, Nathan Froyd, 2009/11/23
- [Qemu-devel] [PATCH 02/11] target-mips: add new HFLAGs for JALX and 16/32-bit delay slots, Nathan Froyd, 2009/11/23
- [Qemu-devel] [PATCH 06/11] target-mips: add gen_base_offset_addr, Nathan Froyd, 2009/11/23
- [Qemu-devel] [PATCH 11/11] target-mips: add copyright notice for mips16 work, Nathan Froyd, 2009/11/23
- [Qemu-devel] [PATCH 08/11] target-mips: add enums for MIPS16 opcodes, Nathan Froyd, 2009/11/23
- [Qemu-devel] [PATCH 05/11] target-mips: make gen_compute_branch 16/32-bit-aware,
Nathan Froyd <=
- [Qemu-devel] [PATCH 10/11] gdbstub: add MIPS16 support, Nathan Froyd, 2009/11/23
- Re: [Qemu-devel] [PATCH 00/11] target-mips: add mips16 support, Aurelien Jarno, 2009/11/28