[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 3/6] target-alpha: Reduce internal processor registe
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 3/6] target-alpha: Reduce internal processor registers for user-mode. |
Date: |
Mon, 4 Jan 2010 11:19:14 -0800 |
The existing set of IPRs is totally irrelevant to user-mode emulation.
Indeed, they most are irrelevant to implementing kernel-mode emulation,
and would only be relevant to PAL-mode emulation, which I suspect that
no one will ever attempt.
Reducing the set of processor registers reduces the size of the CPU state.
Signed-off-by: Richard Henderson <address@hidden>
---
linux-user/main.c | 4 +---
target-alpha/cpu.h | 6 ++++++
target-alpha/translate.c | 45 +++++++++++++++++++++++++++------------------
3 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index a0d8ce7..91e5009 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3050,10 +3050,8 @@ int main(int argc, char **argv, char **envp)
for(i = 0; i < 28; i++) {
env->ir[i] = ((abi_ulong *)regs)[i];
}
- env->ipr[IPR_USP] = regs->usp;
- env->ir[30] = regs->usp;
+ env->ir[IR_SP] = regs->usp;
env->pc = regs->pc;
- env->unique = regs->unique;
}
#elif defined(TARGET_CRIS)
{
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 4722415..3728d83 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -193,6 +193,11 @@ enum {
/* Internal processor registers */
/* XXX: TOFIX: most of those registers are implementation dependant */
enum {
+#if defined(CONFIG_USER_ONLY)
+ IPR_EXC_ADDR,
+ IPR_EXC_SUM,
+ IPR_EXC_MASK,
+#else
/* Ebox IPRs */
IPR_CC = 0xC0, /* 21264 */
IPR_CC_CTL = 0xC1, /* 21264 */
@@ -306,6 +311,7 @@ enum {
IPR_VPTB,
IPR_WHAMI,
IPR_ALT_MODE,
+#endif
IPR_LAST,
};
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 87813e7..515c8c7 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2721,7 +2721,6 @@ static const struct cpu_def_t cpu_defs[] = {
CPUAlphaState * cpu_alpha_init (const char *cpu_model)
{
CPUAlphaState *env;
- uint64_t hwpcb;
int implver, amask, i, max;
env = qemu_mallocz(sizeof(CPUAlphaState));
@@ -2752,24 +2751,34 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
#endif
pal_init(env);
+
/* Initialize IPR */
- hwpcb = env->ipr[IPR_PCBB];
- env->ipr[IPR_ASN] = 0;
- env->ipr[IPR_ASTEN] = 0;
- env->ipr[IPR_ASTSR] = 0;
- env->ipr[IPR_DATFX] = 0;
- /* XXX: fix this */
- // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
- // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
- // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
- // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
- env->ipr[IPR_FEN] = 0;
- env->ipr[IPR_IPL] = 31;
- env->ipr[IPR_MCES] = 0;
- env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
- // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
- env->ipr[IPR_SISR] = 0;
- env->ipr[IPR_VIRBND] = -1ULL;
+#if defined (CONFIG_USER_ONLY)
+ env->ipr[IPR_EXC_ADDR] = 0;
+ env->ipr[IPR_EXC_SUM] = 0;
+ env->ipr[IPR_EXC_MASK] = 0;
+#else
+ {
+ uint64_t hwpcb;
+ hwpcb = env->ipr[IPR_PCBB];
+ env->ipr[IPR_ASN] = 0;
+ env->ipr[IPR_ASTEN] = 0;
+ env->ipr[IPR_ASTSR] = 0;
+ env->ipr[IPR_DATFX] = 0;
+ /* XXX: fix this */
+ // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
+ // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
+ // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
+ // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
+ env->ipr[IPR_FEN] = 0;
+ env->ipr[IPR_IPL] = 31;
+ env->ipr[IPR_MCES] = 0;
+ env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
+ // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
+ env->ipr[IPR_SISR] = 0;
+ env->ipr[IPR_VIRBND] = -1ULL;
+ }
+#endif
qemu_init_vcpu(env);
return env;
--
1.6.5.2
[Qemu-devel] [PATCH 2/6] target-alpha: Split up FPCR value into separate fields., Richard Henderson, 2010/01/05
[Qemu-devel] [PATCH 6/6] target-alpha: Implement IEEE FP qualifiers., Richard Henderson, 2010/01/05
Re: [Qemu-devel] [PATCH 0/6] target-alpha: fpu qualifiers, round 2, Richard Henderson, 2010/01/26