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[Qemu-devel] [PATCH 2/9] sparc64: trace pstate and global register set c
From: |
Igor V. Kovalenko |
Subject: |
[Qemu-devel] [PATCH 2/9] sparc64: trace pstate and global register set changes |
Date: |
Thu, 07 Jan 2010 23:28:00 +0300 |
User-agent: |
StGit/0.15 |
From: Igor V. Kovalenko <address@hidden>
Signed-off-by: Igor V. Kovalenko <address@hidden>
---
target-sparc/op_helper.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index fd3286d..1d3adef 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -11,6 +11,7 @@
//#define DEBUG_UNASSIGNED
//#define DEBUG_ASI
//#define DEBUG_PCALL
+//#define DEBUG_PSTATE
#ifdef DEBUG_MMU
#define DPRINTF_MMU(fmt, ...) \
@@ -31,6 +32,13 @@
do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
#endif
+#ifdef DEBUG_PSTATE
+#define DPRINTF_PSTATE(fmt, ...) \
+ do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
+#endif
+
#ifdef TARGET_SPARC64
#ifndef TARGET_ABI32
#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
@@ -3244,6 +3252,12 @@ static inline uint64_t *get_gregset(uint32_t pstate)
{
switch (pstate) {
default:
+ DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
+ pstate,
+ (pstate & PS_IG) ? " IG" : "",
+ (pstate & PS_MG) ? " MG" : "",
+ (pstate & PS_AG) ? " AG" : "");
+ /* pass through to normal set of global registers */
case 0:
return env->bgregs;
case PS_AG:
@@ -3269,12 +3283,18 @@ static inline void change_pstate(uint32_t new_pstate)
new_pstate_regs = new_pstate & 0xc01;
if (new_pstate_regs != pstate_regs) {
+ DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
+ pstate_regs, new_pstate_regs);
// Switch global register bank
src = get_gregset(new_pstate_regs);
dst = get_gregset(pstate_regs);
memcpy32(dst, env->gregs);
memcpy32(env->gregs, src);
}
+ else {
+ DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
+ new_pstate_regs);
+ }
env->pstate = new_pstate;
}
- [Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 1/9] sparc64: change_pstate should have 32bit argument, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 2/9] sparc64: trace pstate and global register set changes,
Igor V. Kovalenko <=
- [Qemu-devel] [PATCH 4/9] sparc64: use helper_wrpil to check pending irq on write, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 3/9] sparc64: add PIL to cpu state dump, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 5/9] sparc64: check for pending irq when pil, pstate or softint is changed, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 6/9] sparc64: add macros to deal with softint and timer interrupt, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 7/9] sparc64: move cpu_interrupts_enabled to cpu.h, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 8/9] sparc64: interrupt trap handling, Igor V. Kovalenko, 2010/01/07
- [Qemu-devel] [PATCH 9/9] sparc64: reimplement tick timers, Igor V. Kovalenko, 2010/01/07
- Re: [Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1, Blue Swirl, 2010/01/08