qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH 0/5] tcg-sparc improvements


From: Palle Lyckegaard
Subject: Re: [Qemu-devel] [PATCH 0/5] tcg-sparc improvements
Date: Mon, 11 Jan 2010 20:41:52 +0000 (UTC)
User-agent: Alpine 2.01 (NEB 1266 2009-07-14)

On Mon, 11 Jan 2010, Richard Henderson wrote:


Richard Henderson (5):
 tcg-sparc: Add tcg_out_arithc.
 tcg-sparc: Implement add2, sub2, mulu2.
 tcg-sparc: Do not remove %o[012] from 'r' constraint.
 tcg-sparc: Implement division properly.
 tcg-sparc: Implement ext32[su]_i64



Great work :-) Now the NetBSD malta kernel boots using qemu-system-mips on a sparc target!

log:

uname -a
SunOS opensolaris 5.11 snv_111b sun4u sparc SUNW,Ultra-5_10 Solaris

./mips-softmmu/qemu-system-mips --kernel ../../netbsd_malta -m 64 -nographic

MIPS32/64 params: cpu arch: 32
MIPS32/64 params: TLB entries: 16
MIPS32/64 params: Icache: line = 16, total = 2048, ways = 2
                 sets = 64
MIPS32/64 params: Dcache: line = 16, total = 2048, ways = 2
                 sets = 64
  picache_stride    = 1024
  picache_loopcount = 2
  pdcache_stride    = 1024
  pdcache_loopcount = 2
[ Kernel symbol table missing! ]
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 5.0.1 (MALTA) #0: Wed Jul 29 19:36:39 UTC 2009

address@hidden:/home/builds/ab/netbsd-5-0-1-RELEASE/evbmips-mipseb/200907292356Z-obj/home/builds/ab/netbsd-5-0-1-RELEASE/src/sys/arch/evbmips/compile/MALTA
total memory = 65536 KB
avail memory = 59460 KB
mainbus0 (root)
cpu0 at mainbus0: 2152.04MHz (hz cycles = 10760233, delay divisor = 1076)
cpu0: MIPS 24K (0x19300) Rev. 0 with software emulated floating point
cpu0: 2KB/16B 2-way set-associative L1 Instruction cache, 16 TLB entries
cpu0: 2KB/16B 2-way set-associative write-back L1 Data cache
gt0 at mainbus0 addr 0x1be00000
pci0 at gt0





reply via email to

[Prev in Thread] Current Thread [Next in Thread]