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[Qemu-devel] [PATCH 4/4] target-arm: neon fix
From: |
Riku Voipio |
Subject: |
[Qemu-devel] [PATCH 4/4] target-arm: neon fix |
Date: |
Fri, 5 Feb 2010 15:52:31 +0000 |
From: Juha Riihimäki <address@hidden>
add an extra check in "two registers and a shift" to ensure element
size decoding logic cannot fail.
Signed-off-by: Juha Riihimäki <address@hidden>
Signed-off-by: Riku Voipio <address@hidden>
---
target-arm/translate.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 743b846..8bba034 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4567,8 +4567,9 @@ static int disas_neon_data_insn(CPUState * env,
DisasContext *s, uint32_t insn)
size = 3;
} else {
size = 2;
- while (size && (insn & (1 << (size + 19))) == 0)
+ while (size && (insn & (1 << (size + 19))) == 0) {
size--;
+ }
}
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
/* To avoid excessive dumplication of ops we implement shift
--
1.6.5
[Qemu-devel] [PATCH 1/4] target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN, Riku Voipio, 2010/02/05
[Qemu-devel] [PATCH 2/4] target-arm: neon vshll instruction fix, Riku Voipio, 2010/02/05