[Qemu-devel] [PATCH] tcg-mips: Implement setcond2.

[Richard Henderson]

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/mips/tcg-target.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index d181ff1..3a53221 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -643,6 +643,30 @@ static void tcg_out_setcond(TCGContext *s, int cond, int 
ret,
     }
 }
 
+static void tcg_out_setcond2(TCGContext *s, int cond, int ret,
+                             int al, int ah, int bl, int bh)
+{
+    switch (cond) {
+    case TCG_COND_EQ:
+        tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_T0, al, bl);
+        tcg_out_setcond(s, TCG_COND_EQ, ret, ah, bh);
+        tcg_out_opc_reg(s, OPC_AND, ret, ret, TCG_REG_T0);
+        break;
+    case TCG_COND_NE:
+        tcg_out_setcond(s, TCG_COND_NE, TCG_REG_T0, al, bl);
+        tcg_out_setcond(s, TCG_COND_NE, ret, ah, bh);
+        tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_T0);
+        break;
+    default:
+        tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_REG_T0, al, bl);
+        tcg_out_setcond(s, TCG_COND_EQ, TCG_REG_AT, ah, bh);
+        tcg_out_opc_reg(s, OPC_AND, TCG_REG_T0, TCG_REG_T0, TCG_REG_AT);
+        tcg_out_setcond(s, cond, ret, ah, bh);
+        tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_REG_T0);
+        break;
+    }
+}
+
 #if defined(CONFIG_SOFTMMU)
 
 #include "../../softmmu_defs.h"
@@ -1218,6 +1242,10 @@ static inline void tcg_out_op(TCGContext *s, int opc,
     case INDEX_op_setcond_i32:
         tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
         break;
+    case INDEX_op_setcond2_i32:
+        tcg_out_setcond2(s, args[5], args[0], args[1], args[2],
+                         args[3], args[4]);
+        break;
 
     case INDEX_op_qemu_ld8u:
         tcg_out_qemu_ld(s, args, 0);
@@ -1297,6 +1325,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
     { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
     { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJZ", "rJZ" } },
     { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
+    { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
 
 #if TARGET_LONG_BITS == 32
     { INDEX_op_qemu_ld8u, { "L", "lZ" } },
-- 
1.6.6