Re: [Qemu-devel] [PATCH] target-ppc: fix SPE evsplat* instructions

[Aurelien Jarno]

On Tue, Feb 23, 2010 at 12:21:31PM -0800, Nathan Froyd wrote:
> The shifts in the gen_evsplat* functions were expecting rA to be masked,
> not extracted, and so used the wrong shift amounts to sign-extend or pad
> with zeroes.
> 
> Signed-off-by: Nathan Froyd <address@hidden>

Thanks, applied.

> ---
>  target-ppc/translate.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index d4e81ce..0b11fda 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx)
>  }
>  static inline void gen_evsplati(DisasContext *ctx)
>  {
> -    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
> +    uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
>  
>  #if defined(TARGET_PPC64)
>      tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
> @@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx)
>  }
>  static inline void gen_evsplatfi(DisasContext *ctx)
>  {
> -    uint64_t imm = rA(ctx->opcode) << 11;
> +    uint64_t imm = rA(ctx->opcode) << 27;
>  
>  #if defined(TARGET_PPC64)
>      tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
> -- 
> 1.6.3.2
> 
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net