[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] Re: Regression: segfault on ARM host
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] Re: Regression: segfault on ARM host |
Date: |
Tue, 2 Mar 2010 01:05:29 +0100 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
On Mon, Mar 01, 2010 at 11:33:23PM +0100, Paolo Bonzini wrote:
> On 03/01/2010 10:33 PM, Aurelien Jarno wrote:
>> While trying to implement setcond on TCG ARM, I have discovered it does
>> not work anymore. I have bisected this regression to:
>>
>> commit 6113d6d3169393c323ac4c82d756a850145a5e7a
>> Author: Paolo Bonzini<address@hidden>
>> Date: Fri Jan 15 09:42:09 2010 +0100
>>
>> change while to if
>>
>> The while loop will be executed exactly 0 or 1 times, depending on
>> env->exit_request.
>>
>> Signed-off-by: Paolo Bonzini<address@hidden>
>> Signed-off-by: Anthony Liguori<address@hidden>
>>
>> The assertion is actually triggered. When the next patch removing the
>> assertion is also applied it segfaults instead.
>
> Looks like a race. The only piece of logic that is changed by that
> commit is reverted in the attached patch, can you try it? If it passes,
> I can resubmit with S-o-b.
Unfortunately it doesn't work.
> If it doesn't pass, I wonder whether the while loop was there to trick
> the compiler into not optimizing something. Seems a bit too clever
> though.
>
It looks like it is the case. Just replacing the if by a while in your
patch make it working again. But I do wonder what this trick is actually
preventing, as there is probably a better way to prevent that.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net