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From: | Paul Brook |
Subject: | Re: [Qemu-devel] [PATCH] Inter-VM shared memory PCI device |
Date: | Mon, 8 Mar 2010 13:04:45 +0000 |
User-agent: | KMail/1.12.4 (Linux/2.6.32-trunk-amd64; KDE/4.3.4; x86_64; ; ) |
> However, coherence could be made host-type-independent by the host > mapping and unampping pages, so that each page is only mapped into one > guest (or guest CPU) at a time. Just like some clustering filesystems > do to maintain coherence. You're assuming that a TLB flush implies a write barrier, and a TLB miss implies a read barrier. I'd be surprised if this were true in general. Paul
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