Re: [Qemu-devel] [PATCH 09/10] target-alpha: Implement load-locked/store-conditional properly.

[Jamie Lokier]

Richard Henderson wrote:
> On 03/25/2010 06:39 AM, Nathan Froyd wrote:
> > On Wed, Mar 24, 2010 at 05:11:43PM -0700, Richard Henderson wrote:
> >> Use __sync_bool_compare_and_swap to yield correctly atomic results.
> >> As yet, this assumes running on an strict-memory-ordering host (i.e. x86),
> >> since we're still "implementing" the memory-barrier instructions as nops.
> > 
> > Did the approach taken by other targets (arm/mips/ppc) not work on
> > Alpha?
> 
> Mips doesn't even pretend to be atomic.
> 
> Powerpc and Arm -- if I've got this straight -- use some sort of 
> stop-the-world
> mutex+condition and then perform the compare-and-exchange by hand.  I can't
> see how that's better than using an actual compare-and-exchange provided by
> the host cpu.  In fact, I'm mildly horrified by the prospect.

As I've just written with an example elsewhere on this thread,
compare-and-exchange is insufficient to properly emulate ll/sc on some
targets archs, when used with certain algorithms.  I believe ARM is
one such; I don't know about any of the others.

But in nearly all cases, if not all the ones actually seen, it should
be trivial to scan the guest instruction sequence between load-locked
and store-conditional, and confirm that there's no funny business
(non-register operations) in between that would prevent
compare-exchange from emulating it correctly.

So stop-the-world ought to remain in, but only as a last resort to be
used when the ll/sc sequence doesn't pass the no-funny-business test.

The example I gave might even be usable to test it.

-- Jamie