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[Qemu-devel] [PATCH 09/18] tcg/arm: add rotation ops
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 09/18] tcg/arm: add rotation ops |
Date: |
Wed, 7 Apr 2010 19:51:16 +0200 |
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/arm/tcg-target.c | 19 +++++++++++++++++++
tcg/arm/tcg-target.h | 2 +-
2 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 3360c23..4290c4f 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1370,11 +1370,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
case INDEX_op_sar_i32:
c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
+ goto gen_shift32;
+ case INDEX_op_rotr_i32:
+ c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
+ SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
/* Fall through. */
gen_shift32:
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
break;
+ case INDEX_op_rotl_i32:
+ if (const_args[2]) {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
+ ((0x20 - args[2]) & 0x1f) ?
+ SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
+ SHIFT_IMM_LSL(0));
+ } else {
+ tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
+ SHIFT_REG_ROR(TCG_REG_R8));
+ }
+ break;
+
case INDEX_op_brcond_i32:
if (const_args[1]) {
int rot;
@@ -1523,6 +1540,8 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
+ { INDEX_op_rotl_i32, { "r", "r", "ri" } },
+ { INDEX_op_rotr_i32, { "r", "r", "ri" } },
{ INDEX_op_brcond_i32, { "r", "rI" } },
{ INDEX_op_setcond_i32, { "r", "r", "rI" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 334edfa..bc08f91 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -66,7 +66,7 @@ enum {
// #define TCG_TARGET_HAS_bswap32_i32
#define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_neg_i32
-// #define TCG_TARGET_HAS_rot_i32
+#define TCG_TARGET_HAS_rot_i32
#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
--
1.7.0.4
- [Qemu-devel] [PATCH 0/18] tcg/arm: cleanup and improvements, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 02/18] tcg/arm: explicitely list clobbered/reserved regs, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 01/18] tcg/arm: remove SAVE_LR code, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 05/18] tcg/arm: align 64-bit arguments in function calls, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 09/18] tcg/arm: add rotation ops,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 11/18] tcg/arm: add bswap ops, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 08/18] tcg/arm: use the blx instruction when possible, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 06/18] tcg/arm: add defines for the allowed instructions set, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 03/18] tcg/arm: remove store signed functions, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 04/18] tcg/arm: replace integer values by registers enum, Aurelien Jarno, 2010/04/07