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[Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops |
Date: |
Sat, 10 Apr 2010 03:32:59 +0200 |
Add an bswap16 and bswap32 ops, either using the rev and rev16
instructions on ARMv6+ or shifts and logical operations on previous
ARM versions. In both cases the result use less instructions than
the pure TCG version.
These ops are also needed by the qemu_ld/st functions.
v1 -> v2:
- simplify the code as suggested by Paul Brook
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/arm/tcg-target.c | 42 ++++++++++++++++++++++++++++++++++++++++++
tcg/arm/tcg-target.h | 4 ++--
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 1bff87d..e009291 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -527,6 +527,38 @@ static inline void tcg_out_ext16u(TCGContext *s, int cond,
}
}
+static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* rev16 */
+ tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
+ tcg_out_dat_reg(s, cond, ARITH_ORR,
+ rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
+ }
+}
+
+static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
+{
+ if (use_armv6_instructions) {
+ /* rev */
+ tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
+ } else {
+ tcg_out_dat_reg(s, cond, ARITH_EOR,
+ TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
+ tcg_out_dat_imm(s, cond, ARITH_BIC,
+ TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
+ tcg_out_dat_reg(s, cond, ARITH_MOV,
+ rd, 0, rn, SHIFT_IMM_ROR(8));
+ tcg_out_dat_reg(s, cond, ARITH_EOR,
+ rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
+ }
+}
+
static inline void tcg_out_ld32_12(TCGContext *s, int cond,
int rd, int rn, tcg_target_long im)
{
@@ -1544,6 +1576,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_out_qemu_st(s, COND_AL, args, 3);
break;
+ case INDEX_op_bswap16_i32:
+ tcg_out_bswap16(s, COND_AL, args[0], args[1]);
+ break;
+ case INDEX_op_bswap32_i32:
+ tcg_out_bswap32(s, COND_AL, args[0], args[1]);
+ break;
+
case INDEX_op_ext8s_i32:
tcg_out_ext8s(s, COND_AL, args[0], args[1]);
break;
@@ -1631,6 +1670,9 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
#endif
+ { INDEX_op_bswap16_i32, { "r", "r" } },
+ { INDEX_op_bswap32_i32, { "r", "r" } },
+
{ INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } },
{ INDEX_op_ext16u_i32, { "r", "r" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 1f6d665..d8d7d94 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -62,8 +62,8 @@ enum {
#define TCG_TARGET_HAS_ext16s_i32
#undef TCG_TARGET_HAS_ext8u_i32 /* and r0, r1, #0xff */
#define TCG_TARGET_HAS_ext16u_i32
-// #define TCG_TARGET_HAS_bswap16_i32
-// #define TCG_TARGET_HAS_bswap32_i32
+#define TCG_TARGET_HAS_bswap16_i32
+#define TCG_TARGET_HAS_bswap32_i32
#define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_neg_i32
#define TCG_TARGET_HAS_rot_i32
--
1.7.0.4
- [Qemu-devel] [PATCH v2 05/18] tcg/arm: align 64-bit arguments in function calls, (continued)
- [Qemu-devel] [PATCH v2 05/18] tcg/arm: align 64-bit arguments in function calls, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 01/18] tcg/arm: remove SAVE_LR code, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 04/18] tcg/arm: replace integer values by registers enum, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 02/18] tcg/arm: explicitely list clobbered/reserved regs, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 07/18] tcg/arm: sxtb and sxth are available starting with ARMv6, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 03/18] tcg/arm: remove store signed functions, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 08/18] tcg/arm: use the blx instruction when possible, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 09/18] tcg/arm: add rotation ops, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 06/18] tcg/arm: add variables to define the allowed instructions set, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 10/18] tcg/arm: add ext16u op, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 11/18] tcg/arm: add bswap ops,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 12/18] tcg/arm: remove conditional argument for qemu_ld/st, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 16/18] tcg/arm: fix argument alignment in qemu_st64, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 18/18] tcg/arm: don't try to load constants using pc, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 17/18] tcg/arm: optimize register allocation order, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 13/18] tcg/arm: use ext* ops in qemu_ld, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 15/18] tcg/arm: remove useless register tests in qemu_ld/st, Aurelien Jarno, 2010/04/09
- [Qemu-devel] [PATCH v2 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed, Aurelien Jarno, 2010/04/09