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[Qemu-devel] [PATCH, RFC 2/4] Convert PCI devices to use pci_register_me
From: |
Blue Swirl |
Subject: |
[Qemu-devel] [PATCH, RFC 2/4] Convert PCI devices to use pci_register_memory() |
Date: |
Sun, 23 May 2010 20:34:39 +0000 |
Signed-off-by: Blue Swirl <address@hidden>
---
hw/cirrus_vga.c | 12 ++++++------
hw/e1000.c | 2 +-
hw/eepro100.c | 2 +-
hw/isa.h | 1 +
hw/isa_mmio.c | 18 ++++++++++++++++--
hw/lsi53c895a.c | 4 ++--
hw/macio.c | 24 ++++++++++++------------
hw/msix.c | 4 ++--
hw/openpic.c | 6 +++---
hw/pcnet.c | 3 ++-
hw/rtl8139.c | 2 +-
hw/sun4u.c | 7 +++++--
hw/usb-ohci.c | 2 +-
hw/vga-pci.c | 4 ++--
hw/vmware_vga.c | 7 +++----
hw/wdt_i6300esb.c | 2 +-
16 files changed, 59 insertions(+), 41 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index ba48289..52e51e0 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -3145,10 +3145,10 @@ static void cirrus_pci_lfb_map(PCIDevice *d,
int region_num,
CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
/* XXX: add byte swapping apertures */
- cpu_register_physical_memory(addr, s->vga.vram_size,
- s->cirrus_linear_io_addr);
- cpu_register_physical_memory(addr + 0x1000000, 0x400000,
- s->cirrus_linear_bitblt_io_addr);
+ pci_register_memory(d->bus, addr, s->vga.vram_size,
+ s->cirrus_linear_io_addr);
+ pci_register_memory(d->bus, addr + 0x1000000, 0x400000,
+ s->cirrus_linear_bitblt_io_addr);
s->vga.map_addr = s->vga.map_end = 0;
s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
@@ -3165,8 +3165,8 @@ static void cirrus_pci_mmio_map(PCIDevice *d,
int region_num,
{
CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
- cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
- s->cirrus_mmio_io_addr);
+ pci_register_memory(d->bus, addr, CIRRUS_PNPMMIO_SIZE,
+ s->cirrus_mmio_io_addr);
}
static void pci_cirrus_write_config(PCIDevice *d,
diff --git a/hw/e1000.c b/hw/e1000.c
index 96d045d..89b503a 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1032,7 +1032,7 @@ e1000_mmio_map(PCIDevice *pci_dev, int region_num,
DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
addr, size);
- cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
+ pci_register_memory(pci_dev->bus, addr, PNPMMIO_SIZE, d->mmio_index);
qemu_register_coalesced_mmio(addr, excluded_regs[0]);
for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
diff --git a/hw/eepro100.c b/hw/eepro100.c
index a74d834..9e64251 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1623,7 +1623,7 @@ static void pci_mmio_map(PCIDevice * pci_dev,
int region_num,
assert(region_num == 0 || region_num == 2);
/* Map control / status registers and flash. */
- cpu_register_physical_memory(addr, size, s->mmio_index);
+ pci_register_memory(pci_dev->bus, addr, size, s->mmio_index);
s->region[region_num] = addr;
}
diff --git a/hw/isa.h b/hw/isa.h
index aaf0272..e40a1d4 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -33,6 +33,7 @@ ISADevice *isa_create_simple(const char *name);
extern target_phys_addr_t isa_mem_base;
void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be);
+int pci_isa_mmio_init(target_phys_addr_t base, target_phys_addr_t
size, int be);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index 66bdd2c..01dfab9 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -125,7 +125,8 @@ static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
static int isa_mmio_iomemtype = 0;
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
+static int isa_mmio_memtype(target_phys_addr_t base, target_phys_addr_t size,
+ int be)
{
if (!isa_mmio_iomemtype) {
if (be) {
@@ -138,5 +139,18 @@ void isa_mmio_init(target_phys_addr_t base,
target_phys_addr_t size, int be)
NULL);
}
}
- cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
+ return isa_mmio_iomemtype;
+}
+
+void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
+{
+ int isa;
+
+ isa = isa_mmio_memtype(base, size, be);
+ cpu_register_physical_memory(base, size, isa);
+}
+
+int pci_isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
+{
+ return isa_mmio_memtype(base, size, be);
}
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index f5a91ba..3386148 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -2015,7 +2015,7 @@ static void lsi_ram_mapfunc(PCIDevice *pci_dev,
int region_num,
DPRINTF("Mapping ram at %08"FMT_PCIBUS"\n", addr);
s->script_ram_base = addr;
- cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
+ pci_register_memory(pci_dev->bus, addr + 0, 0x2000, s->ram_io_addr);
}
static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
@@ -2024,7 +2024,7 @@ static void lsi_mmio_mapfunc(PCIDevice *pci_dev,
int region_num,
LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
DPRINTF("Mapping registers at %08"FMT_PCIBUS"\n", addr);
- cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
+ pci_register_memory(pci_dev->bus, addr + 0, 0x400, s->mmio_io_addr);
}
static void lsi_scsi_reset(DeviceState *dev)
diff --git a/hw/macio.c b/hw/macio.c
index e92e82a..11407b3 100644
--- a/hw/macio.c
+++ b/hw/macio.c
@@ -49,30 +49,30 @@ static void macio_map (PCIDevice *pci_dev, int region_num,
if (macio_state->pic_mem_index >= 0) {
if (macio_state->is_oldworld) {
/* Heathrow PIC */
- cpu_register_physical_memory(addr + 0x00000, 0x1000,
- macio_state->pic_mem_index);
+ pci_register_memory(pci_dev->bus, addr + 0x00000, 0x1000,
+ macio_state->pic_mem_index);
} else {
/* OpenPIC */
- cpu_register_physical_memory(addr + 0x40000, 0x40000,
- macio_state->pic_mem_index);
+ pci_register_memory(pci_dev->bus, addr + 0x40000, 0x40000,
+ macio_state->pic_mem_index);
}
}
if (macio_state->dbdma_mem_index >= 0) {
- cpu_register_physical_memory(addr + 0x08000, 0x1000,
- macio_state->dbdma_mem_index);
+ pci_register_memory(pci_dev->bus, addr + 0x08000, 0x1000,
+ macio_state->dbdma_mem_index);
}
if (macio_state->escc_mem_index >= 0) {
- cpu_register_physical_memory(addr + 0x13000, ESCC_SIZE << 4,
- macio_state->escc_mem_index);
+ pci_register_memory(pci_dev->bus, addr + 0x13000, ESCC_SIZE << 4,
+ macio_state->escc_mem_index);
}
if (macio_state->cuda_mem_index >= 0) {
- cpu_register_physical_memory(addr + 0x16000, 0x2000,
- macio_state->cuda_mem_index);
+ pci_register_memory(pci_dev->bus, addr + 0x16000, 0x2000,
+ macio_state->cuda_mem_index);
}
for (i = 0; i < macio_state->nb_ide; i++) {
if (macio_state->ide_mem_index[i] >= 0) {
- cpu_register_physical_memory(addr + 0x1f000 + (i * 0x1000), 0x1000,
- macio_state->ide_mem_index[i]);
+ pci_register_memory(pci_dev->bus, addr + 0x1f000 + (i * 0x1000),
+ 0x1000, macio_state->ide_mem_index[i]);
}
}
if (macio_state->nvram != NULL)
diff --git a/hw/msix.c b/hw/msix.c
index 2ca0900..0328a4a 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -233,8 +233,8 @@ void msix_mmio_map(PCIDevice *d, int region_num,
return;
if (size <= offset)
return;
- cpu_register_physical_memory(addr + offset, size - offset,
- d->msix_mmio_index);
+ pci_register_memory(d->bus, addr + offset, size - offset,
+ d->msix_mmio_index);
}
static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
diff --git a/hw/openpic.c b/hw/openpic.c
index ac21993..3e5f458 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1032,12 +1032,12 @@ static void openpic_map(PCIDevice *pci_dev,
int region_num,
/* Per CPU registers */
DPRINTF("Register OPENPIC dst %08x => %08x\n",
addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
- cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
+ pci_register_memory(pci_dev->bus, addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(openpic_src_read,
openpic_src_write);
- cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
- opp_io_memory);
+ pci_register_memory(pci_dev->bus, isu_base, 0x20 * (EXT_IRQ + 2),
+ opp_io_memory);
#endif
}
diff --git a/hw/pcnet.c b/hw/pcnet.c
index 5e63eb5..0ead646 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -1925,7 +1925,8 @@ static void pcnet_mmio_map(PCIDevice *pci_dev,
int region_num,
addr, size);
#endif
- cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE,
d->state.mmio_index);
+ pci_register_memory(pci_dev->bus, addr, PCNET_PNPMMIO_SIZE,
+ d->state.mmio_index);
}
static void pci_physical_memory_write(void *dma_opaque,
target_phys_addr_t addr,
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 72e2242..deae6ae 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -3274,7 +3274,7 @@ static void rtl8139_mmio_map(PCIDevice *pci_dev,
int region_num,
{
RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
- cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
+ pci_register_memory(pci_dev->bus, addr + 0, 0x100,
s->rtl8139_mmio_io_addr);
}
static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
diff --git a/hw/sun4u.c b/hw/sun4u.c
index e9a1e23..71c616a 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -520,14 +520,17 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
+ int isamm;
EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
region_num, addr);
switch (region_num) {
case 0:
- isa_mmio_init(addr, 0x1000000, 1);
+ isamm = pci_isa_mmio_init(addr, 0x1000000, 1);
+ pci_register_memory(pci_dev->bus, addr, size, isamm);
break;
case 1:
- isa_mmio_init(addr, 0x800000, 1);
+ isamm = pci_isa_mmio_init(addr, 0x800000, 1);
+ pci_register_memory(pci_dev->bus, addr, size, isamm);
break;
}
}
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index 9f80e15..c891aba 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1717,7 +1717,7 @@ static void ohci_mapfunc(PCIDevice *pci_dev, int i,
pcibus_t addr, pcibus_t size, int type)
{
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, pci_dev);
- cpu_register_physical_memory(addr, size, ohci->state.mem);
+ pci_register_memory(pci_dev->bus, addr, size, ohci->state.mem);
}
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index eef78ed..6135bb2 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -53,9 +53,9 @@ static void vga_map(PCIDevice *pci_dev, int region_num,
PCIVGAState *d = (PCIVGAState *)pci_dev;
VGACommonState *s = &d->vga;
if (region_num == PCI_ROM_SLOT) {
- cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
+ pci_register_memory(pci_dev->bus, addr, s->bios_size, s->bios_offset);
} else {
- cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
+ pci_register_memory(pci_dev->bus, addr, s->vram_size, s->vram_offset);
s->map_addr = addr;
s->map_end = addr + s->vram_size;
vga_dirty_log_start(s);
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index e709369..7d5d795 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1182,8 +1182,8 @@ static void pci_vmsvga_map_mem(PCIDevice
*pci_dev, int region_num,
#else
iomemtype = s->vga.vram_offset | IO_MEM_RAM;
#endif
- cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
- iomemtype);
+ pci_register_memory(pci_dev->bus, s->vram_base, s->vga.vram_size,
+ iomemtype);
s->vga.map_addr = addr;
s->vga.map_end = addr + s->vga.vram_size;
@@ -1199,8 +1199,7 @@ static void pci_vmsvga_map_fifo(PCIDevice
*pci_dev, int region_num,
s->fifo_base = addr;
iomemtype = s->fifo_offset | IO_MEM_RAM;
- cpu_register_physical_memory(s->fifo_base, s->fifo_size,
- iomemtype);
+ pci_register_memory(pci_dev->bus, s->fifo_base, s->fifo_size, iomemtype);
}
static int pci_vmsvga_initfn(PCIDevice *dev)
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index be0e89e..ccdd495 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -362,7 +362,7 @@ static void i6300esb_map(PCIDevice *dev, int region_num,
addr, size, type);
io_mem = cpu_register_io_memory(mem_read, mem_write, d);
- cpu_register_physical_memory (addr, 0x10, io_mem);
+ pci_register_memory(dev->bus, addr, 0x10, io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
}
--
1.6.2.4
- [Qemu-devel] [PATCH, RFC 2/4] Convert PCI devices to use pci_register_memory(),
Blue Swirl <=