What's the benefit of exposing this information to the guest?
That is mostly to propagate the cache size and organization parameters
to the guest:
>> +/* safe CPUID leafs to propagate to guest if -cpu host is specified
>> + * Intel defined leafs:
>> + * Cache descriptors (0x02)
>> + * Deterministic cache parameters (0x04)
>> + * Monitor/MWAIT parameters (0x05)
>> + *
>> + * AMD defined leafs:
>> + * L1 Cache and TLB (0x05)
>> + * L2+L3 TLB (0x06)
>> + * LongMode address size (0x08)
>> + * 1GB page TLB (0x19)
>> + * Performance optimization (0x1A)
>> + */
Since at least L1 and L2 caches are mostly private to vCPUs, I see no
reason to disguise them.