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[Qemu-devel] [PATCH 05/62] tcg-s390: Move opcode defines to tcg-target.c
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/62] tcg-s390: Move opcode defines to tcg-target.c. |
Date: |
Thu, 27 May 2010 13:45:47 -0700 |
In addition to being the Right Thing, some of the RR_* defines
conflict with RR_* enumerations in target-mips/cpu.h.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/s390/tcg-target.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++
tcg/s390/tcg-target.h | 80 ------------------------------------------------
2 files changed, 81 insertions(+), 80 deletions(-)
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index f0013e7..1f961ad 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -33,6 +33,87 @@
do { } while (0)
#endif
+#define TCG_CT_CONST_S16 0x100
+#define TCG_CT_CONST_U12 0x200
+
+#define E3_LG 0x04
+#define E3_LRVG 0x0f
+#define E3_LGF 0x14
+#define E3_LGH 0x15
+#define E3_LLGF 0x16
+#define E3_LRV 0x1e
+#define E3_LRVH 0x1f
+#define E3_CG 0x20
+#define E3_STG 0x24
+#define E3_STRVG 0x2f
+#define E3_STRV 0x3e
+#define E3_STRVH 0x3f
+#define E3_STHY 0x70
+#define E3_STCY 0x72
+#define E3_LGB 0x77
+#define E3_LLGC 0x90
+#define E3_LLGH 0x91
+
+#define B9_LGR 0x04
+#define B9_AGR 0x08
+#define B9_SGR 0x09
+#define B9_MSGR 0x0c
+#define B9_LGFR 0x14
+#define B9_LLGFR 0x16
+#define B9_CGR 0x20
+#define B9_CLGR 0x21
+#define B9_NGR 0x80
+#define B9_OGR 0x81
+#define B9_XGR 0x82
+#define B9_DLGR 0x87
+#define B9_DLR 0x97
+
+#define RR_BASR 0x0d
+#define RR_NR 0x14
+#define RR_CLR 0x15
+#define RR_OR 0x16
+#define RR_XR 0x17
+#define RR_LR 0x18
+#define RR_CR 0x19
+#define RR_AR 0x1a
+#define RR_SR 0x1b
+
+#define A7_AHI 0xa
+#define A7_AHGI 0xb
+
+#define SH64_REG_NONE 0x00 /* use immediate only (not R0!) */
+#define SH64_SRAG 0x0a
+#define SH64_SRLG 0x0c
+#define SH64_SLLG 0x0d
+
+#define SH32_REG_NONE 0x00 /* use immediate only (not R0!) */
+#define SH32_SRL 0x08
+#define SH32_SLL 0x09
+#define SH32_SRA 0x0a
+
+#define ST_STH 0x40
+#define ST_STC 0x42
+#define ST_ST 0x50
+
+#define LD_SIGNED 0x04
+#define LD_UINT8 0x00
+#define LD_INT8 (LD_UINT8 | LD_SIGNED)
+#define LD_UINT16 0x01
+#define LD_INT16 (LD_UINT16 | LD_SIGNED)
+#define LD_UINT32 0x02
+#define LD_INT32 (LD_UINT32 | LD_SIGNED)
+#define LD_UINT64 0x03
+#define LD_INT64 (LD_UINT64 | LD_SIGNED)
+
+#define S390_INS_BCR 0x0700
+#define S390_INS_BR (S390_INS_BCR | 0x00f0)
+#define S390_INS_IILH 0xa5020000
+#define S390_INS_LLILL 0xa50f0000
+#define S390_INS_LGHI 0xa7090000
+#define S390_INS_MSR 0xb2520000
+#define S390_INS_LARL 0xc000
+
+
static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R6,
TCG_REG_R7,
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index bd72115..7495258 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -87,86 +87,6 @@ enum {
#define TCG_TARGET_STACK_ALIGN 8
#define TCG_TARGET_CALL_STACK_OFFSET 0
-#define TCG_CT_CONST_S16 0x100
-#define TCG_CT_CONST_U12 0x200
-
-#define E3_LG 0x04
-#define E3_LRVG 0x0f
-#define E3_LGF 0x14
-#define E3_LGH 0x15
-#define E3_LLGF 0x16
-#define E3_LRV 0x1e
-#define E3_LRVH 0x1f
-#define E3_CG 0x20
-#define E3_STG 0x24
-#define E3_STRVG 0x2f
-#define E3_STRV 0x3e
-#define E3_STRVH 0x3f
-#define E3_STHY 0x70
-#define E3_STCY 0x72
-#define E3_LGB 0x77
-#define E3_LLGC 0x90
-#define E3_LLGH 0x91
-
-#define B9_LGR 0x04
-#define B9_AGR 0x08
-#define B9_SGR 0x09
-#define B9_MSGR 0x0c
-#define B9_LGFR 0x14
-#define B9_LLGFR 0x16
-#define B9_CGR 0x20
-#define B9_CLGR 0x21
-#define B9_NGR 0x80
-#define B9_OGR 0x81
-#define B9_XGR 0x82
-#define B9_DLGR 0x87
-#define B9_DLR 0x97
-
-#define RR_BASR 0x0d
-#define RR_NR 0x14
-#define RR_CLR 0x15
-#define RR_OR 0x16
-#define RR_XR 0x17
-#define RR_LR 0x18
-#define RR_CR 0x19
-#define RR_AR 0x1a
-#define RR_SR 0x1b
-
-#define A7_AHI 0xa
-#define A7_AHGI 0xb
-
-#define SH64_REG_NONE 0x00 /* use immediate only (not R0!) */
-#define SH64_SRAG 0x0a
-#define SH64_SRLG 0x0c
-#define SH64_SLLG 0x0d
-
-#define SH32_REG_NONE 0x00 /* use immediate only (not R0!) */
-#define SH32_SRL 0x08
-#define SH32_SLL 0x09
-#define SH32_SRA 0x0a
-
-#define ST_STH 0x40
-#define ST_STC 0x42
-#define ST_ST 0x50
-
-#define LD_SIGNED 0x04
-#define LD_UINT8 0x00
-#define LD_INT8 (LD_UINT8 | LD_SIGNED)
-#define LD_UINT16 0x01
-#define LD_INT16 (LD_UINT16 | LD_SIGNED)
-#define LD_UINT32 0x02
-#define LD_INT32 (LD_UINT32 | LD_SIGNED)
-#define LD_UINT64 0x03
-#define LD_INT64 (LD_UINT64 | LD_SIGNED)
-
-#define S390_INS_BCR 0x0700
-#define S390_INS_BR (S390_INS_BCR | 0x00f0)
-#define S390_INS_IILH 0xa5020000
-#define S390_INS_LLILL 0xa50f0000
-#define S390_INS_LGHI 0xa7090000
-#define S390_INS_MSR 0xb2520000
-#define S390_INS_LARL 0xc000
-
enum {
/* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R10,
--
1.7.0.1
- [Qemu-devel] [PATCH 00/62] s390x tcg target, Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 02/62] add lost chunks from the original patch, Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 03/62] tcg-s390: Only validate CPUTLBEntry for system mode., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 04/62] tcg-s390: Fix tcg_prepare_qemu_ldst for user mode., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 01/62] S390 TCG target, Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 06/62] s390x: Avoid _llseek., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 05/62] tcg-s390: Move opcode defines to tcg-target.c.,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/62] s390x: Don't use a linker script for user-only., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 08/62] tcg-s390: Avoid set-but-not-used werrors., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 09/62] tcg-s390: Mark R0 & R15 reserved., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 11/62] tcg-s390: Move tcg_out_mov up and use it throughout., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 12/62] tcg-s390: Eliminate the S constraint., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 10/62] tcg-s390: R6 is a function argument register, Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 14/62] tcg-s390: Define tcg_target_reg_names., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 13/62] tcg-s390: Add -m64 and -march to s390x compilation., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 16/62] tcg-s390: Compute is_write in cpu_signal_handler., Richard Henderson, 2010/05/27
- [Qemu-devel] [PATCH 19/62] tcg-s390: Fixup qemu_ld/st opcodes., Richard Henderson, 2010/05/27