[Qemu-devel] [PATCH 53/62] tcg-s390: Conditionalize XOR IMMEDIATE instructions.

[Richard Henderson]

The immediate XOR instructions are in the extended-immediate
facility.  Use these only if present.

At the same time, pull the logic to load immediates into registers
into a constraint letter for TCG.

Signed-off-by: Richard Henderson <address@hidden>
---
 tcg/s390/tcg-target.c |   53 +++++++++++++++++++++++++++++++-----------------
 1 files changed, 34 insertions(+), 19 deletions(-)

diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 36d4ad0..084448a 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -39,6 +39,7 @@
 #define TCG_CT_CONST_MULI  0x0800
 #define TCG_CT_CONST_ANDI  0x1000
 #define TCG_CT_CONST_ORI   0x2000
+#define TCG_CT_CONST_XORI  0x4000
 
 #define TCG_TMP0           TCG_REG_R14
 
@@ -363,6 +364,10 @@ static int target_parse_constraint(TCGArgConstraint *ct, 
const char **pct_str)
         ct->ct &= ~TCG_CT_REG;
         ct->ct |= TCG_CT_CONST_ORI;
         break;
+    case 'X':
+        ct->ct &= ~TCG_CT_REG;
+        ct->ct |= TCG_CT_CONST_XORI;
+        break;
     default:
         break;
     }
@@ -459,6 +464,30 @@ static int tcg_match_ori(int ct, tcg_target_long val)
     return 1;
 }
 
+/* Immediates to be used with logical XOR.  This is almost, but not quite,
+   only an optimization.  XOR with immediate is only supported with the
+   extended-immediate facility.  That said, there are a few patterns for
+   which it is better to load the value into a register first.  */
+
+static int tcg_match_xori(int ct, tcg_target_long val)
+{
+    if ((facilities & FACILITY_EXT_IMM) == 0) {
+        return 0;
+    }
+
+    if (ct & TCG_CT_CONST_32) {
+        /* All 32-bit XORs can be performed with 1 48-bit insn.  */
+        return 1;
+    }
+
+    /* Look for negative values.  These are best to load with LGHI.  */
+    if (val < 0 && val == (int32_t)val) {
+        return 0;
+    }
+
+    return 1;
+}
+
 /* Test if a constant matches the constraint. */
 static int tcg_target_const_match(tcg_target_long val,
                                   const TCGArgConstraint *arg_ct)
@@ -502,6 +531,8 @@ static int tcg_target_const_match(tcg_target_long val,
         return tcg_match_andi(ct, val);
     } else if (ct & TCG_CT_CONST_ORI) {
         return tcg_match_ori(ct, val);
+    } else if (ct & TCG_CT_CONST_XORI) {
+        return tcg_match_xori(ct, val);
     }
 
     return 0;
@@ -987,23 +1018,7 @@ static void tgen64_ori(TCGContext *s, TCGReg dest, 
tcg_target_ulong val)
 
 static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
 {
-    tcg_target_long sval = val;
-
-    /* Zero-th, look for no-op.  */
-    if (val == 0) {
-        return;
-    }
-
-    /* First, look for 64-bit values for which it is better to load the
-       value first and perform the xor via registers.  This is true for
-       any 32-bit negative value, where the high 32-bits get flipped too.  */
-    if (sval < 0 && sval == (int32_t)sval) {
-        tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, sval);
-        tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);
-        return;
-    }
-
-    /* Second, perform the xor by parts.  */
+    /* Perform the xor by parts.  */
     if (val & 0xffffffff) {
         tcg_out_insn(s, RIL, XILF, dest, val);
     }
@@ -1813,7 +1828,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
 
     { INDEX_op_and_i32, { "r", "0", "rWA" } },
     { INDEX_op_or_i32, { "r", "0", "rWO" } },
-    { INDEX_op_xor_i32, { "r", "0", "ri" } },
+    { INDEX_op_xor_i32, { "r", "0", "rWX" } },
     { INDEX_op_neg_i32, { "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "0", "Ri" } },
@@ -1874,7 +1889,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
 
     { INDEX_op_and_i64, { "r", "0", "rA" } },
     { INDEX_op_or_i64, { "r", "0", "rO" } },
-    { INDEX_op_xor_i64, { "r", "0", "ri" } },
+    { INDEX_op_xor_i64, { "r", "0", "rX" } },
     { INDEX_op_neg_i64, { "r", "r" } },
 
     { INDEX_op_shl_i64, { "r", "r", "Ri" } },
-- 
1.7.0.1