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[Qemu-devel] [PATCH 6/8] target-mips: add microMIPS exception handler su
From: |
Nathan Froyd |
Subject: |
[Qemu-devel] [PATCH 6/8] target-mips: add microMIPS exception handler support |
Date: |
Tue, 8 Jun 2010 13:30:01 -0700 |
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers. The ISA mode is selectable via a user-writable CP0.Config3
flag.
Signed-off-by: Nathan Froyd <address@hidden>
---
target-mips/cpu.h | 1 +
target-mips/helper.c | 21 +++++++++++++++------
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7285636..c21b8e4 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -363,6 +363,7 @@ struct CPUMIPSState {
#define CP0C2_SA 0
int32_t CP0_Config3;
#define CP0C3_M 31
+#define CP0C3_ISA_ON_EXC 16
#define CP0C3_DSPP 10
#define CP0C3_LPA 7
#define CP0C3_VEIC 6
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8102f03..ea221ab 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -385,6 +385,18 @@ static target_ulong exception_resume_pc (CPUState *env)
return bad_pc;
}
+
+static void set_hflags_for_handler (CPUState *env)
+{
+ /* Exception handlers are entered in 32-bit mode. */
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ /* ...except that microMIPS lets you choose. */
+ if (env->insn_flags & ASE_MICROMIPS) {
+ env->hflags |= (!!(env->CP0_Config3
+ & (1 << CP0C3_ISA_ON_EXC))
+ << MIPS_HFLAG_M16_SHIFT);
+ }
+}
#endif
void do_interrupt (CPUState *env)
@@ -440,8 +452,7 @@ void do_interrupt (CPUState *env)
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480;
- /* Exception handlers are entered in 32-bit mode. */
- env->hflags &= ~(MIPS_HFLAG_M16);
+ set_hflags_for_handler(env);
break;
case EXCP_RESET:
cpu_reset(env);
@@ -461,8 +472,7 @@ void do_interrupt (CPUState *env)
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000;
- /* Exception handlers are entered in 32-bit mode. */
- env->hflags &= ~(MIPS_HFLAG_M16);
+ set_hflags_for_handler(env);
break;
case EXCP_EXT_INTERRUPT:
cause = 0;
@@ -581,8 +591,7 @@ void do_interrupt (CPUState *env)
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}
env->active_tc.PC += offset;
- /* Exception handlers are entered in 32-bit mode. */
- env->hflags &= ~(MIPS_HFLAG_M16);
+ set_hflags_for_handler(env);
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause <<
CP0Ca_EC);
break;
default:
--
1.6.3.2
- [Qemu-devel] [PATCH 0/8] target-mips: add microMIPS ASE support, v3, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 7/8] linux-user: honor low bit of entry PC for MIPS, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 2/8] target-mips: refactor c{, abs}.cond.fmt insns, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 8/8] hw: honor low bit in mipssim machine, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 1/8] target-mips: define constants for magic numbers, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 5/8] target-mips: add microMIPS CPUs, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 3/8] target-mips: mips16 cleanups, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 4/8] target-mips: microMIPS ASE support, Nathan Froyd, 2010/06/08
- [Qemu-devel] [PATCH 6/8] target-mips: add microMIPS exception handler support,
Nathan Froyd <=
- Re: [Qemu-devel] [PATCH 0/8] target-mips: add microMIPS ASE support, v3, Aurelien Jarno, 2010/06/09