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[Qemu-devel] [PATCH v5 1/9] pci: use PCI_DEVFN() where appropriate.
From: |
Isaku Yamahata |
Subject: |
[Qemu-devel] [PATCH v5 1/9] pci: use PCI_DEVFN() where appropriate. |
Date: |
Wed, 23 Jun 2010 16:15:25 +0900 |
Use PCI_DEVFN() and PCI_FUNC_MAX where appropriate.
This patch make it clear that func = 0.
test:
The following object files with/without this patch are stripped and compared.
They remains same.
arm-softmmu/versatile_pci.o
libhw32/ppce500_pci.o
libhw32/unin_pci.o
libhw64/ppce500_pci.o
libhw64/unin_pci.o
mips-softmmu/gt64xxx.o
mips64-softmmu/gt64xxx.o
mips64el-softmmu/gt64xxx.o
mipsel-softmmu/gt64xxx.o
Cc: Aurelien Jarno <address@hidden>
Cc: Yu Liu <address@hidden>
Cc: Paul Brook <address@hidden>
Signed-off-by: Isaku Yamahata <address@hidden>
---
changes v2 -> v3
- split out into PCI_DEVFN() patch and assert patch.
- more test by comparing stripped object.
---
hw/gt64xxx.c | 2 +-
hw/ppce500_pci.c | 3 ++-
hw/unin_pci.c | 12 ++++++------
hw/versatile_pci.c | 2 +-
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 7691e1d..8e2cf14 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1115,7 +1115,7 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
s->pci->bus = pci_register_bus(NULL, "pci",
pci_gt64120_set_irq, pci_gt64120_map_irq,
- pic, 144, 4);
+ pic, PCI_DEVFN(18, 0), 4);
s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
0, NULL, NULL);
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 336d284..f949fe3 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -279,7 +279,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4],
target_phys_addr_t registers)
controller->pci_state.bus = pci_register_bus(NULL, "pci",
mpc85xx_pci_set_irq,
mpc85xx_pci_map_irq,
- pci_irqs, 0x88, 4);
+ pci_irqs, PCI_DEVFN(0x11, 0),
+ 4);
d = pci_register_device(controller->pci_state.bus,
"host bridge", sizeof(PCIDevice),
0, NULL, NULL);
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index f0a773d..0ecf40f 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -228,10 +228,10 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
d = FROM_SYSBUS(UNINState, s);
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq,
- pic, 11 << 3, 4);
+ pic, PCI_DEVFN(11, 0), 4);
#if 0
- pci_create_simple(d->host_state.bus, 11 << 3, "uni-north");
+ pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif
sysbus_mmio_map(s, 0, 0xf2800000);
@@ -240,11 +240,11 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
/* DEC 21154 bridge */
#if 0
/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
- pci_create_simple(d->host_state.bus, 12 << 3, "dec-21154");
+ pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
#endif
/* Uninorth AGP bus */
- pci_create_simple(d->host_state.bus, 11 << 3, "uni-north-agp");
+ pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
dev = qdev_create(NULL, "uni-north-agp");
qdev_init_nofail(dev);
s = sysbus_from_qdev(dev);
@@ -254,7 +254,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
/* Uninorth internal bus */
#if 0
/* XXX: not needed for now */
- pci_create_simple(d->host_state.bus, 14 << 3, "uni-north-pci");
+ pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
dev = qdev_create(NULL, "uni-north-pci");
qdev_init_nofail(dev);
s = sysbus_from_qdev(dev);
@@ -280,7 +280,7 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic)
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq,
- pic, 11 << 3, 4);
+ pic, PCI_DEVFN(11, 0), 4);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 199bc19..a76bdfa 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -127,7 +127,7 @@ static int pci_vpb_init(SysBusDevice *dev)
}
bus = pci_register_bus(&dev->qdev, "pci",
pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
- 11 << 3, 4);
+ PCI_DEVFN(11, 0), 4);
/* ??? Register memory space. */
--
1.6.6.1
- [Qemu-devel] [PATCH v5 0/9] pci: multi-function bit fixes, Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 2/9] pci: insert assert that auto-assigned-address function is single function device., Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 7/9] pci: set multifunction property for normal device., Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 3/9] pci: don't overwrite multi functio bit in pci header type., Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 1/9] pci: use PCI_DEVFN() where appropriate.,
Isaku Yamahata <=
- [Qemu-devel] [PATCH v5 5/9] qdev: implement qdev_prop_set_bit()., Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 9/9] pci: set PCI multi-function bit appropriately., Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 8/9] pci_bridge: make pci bridge aware of pci multi function bit., Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 4/9] pci: remove PCIDeviceInfo::header_type, Isaku Yamahata, 2010/06/23
- [Qemu-devel] [PATCH v5 6/9] pci: introduce multifunction property., Isaku Yamahata, 2010/06/23