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Re: [Qemu-devel] [PATCH v2 0/7] APIC/IOAPIC cleanup


From: malc
Subject: Re: [Qemu-devel] [PATCH v2 0/7] APIC/IOAPIC cleanup
Date: Fri, 20 Aug 2010 14:00:13 +0400 (MSD)
User-agent: Alpine 2.00 (LNX 1167 2008-08-23)

On Thu, 19 Aug 2010, Anthony Liguori wrote:

> On 08/19/2010 05:52 PM, malc wrote:
> > > Yes, but the programming model was different.
> > > 
> > > Look at the PIC compared to the lapic.  The PIC is programmed via pio at a
> > > fixed location.  There is only one PIC and it interacts with the system
> > > just
> > > like all other devices.  IOW, there is no reference to CPUState.
> > >      
> > There are two PICs actually there's a cascade..
> >    
> 
> Technically speaking, originally there was just one and then more IRQs were
> supported by cascading and reserving an IRQ line for supporting cascading.  I
> think you can technical cascade with any IRQ and have more than one slave but
> the historic PC architecture only had one slave AFAIK.

One master + one slave = 2 PICs, i guess you've meant that originally
there was no slave.

[..snip..]

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