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[Qemu-devel] Re: [PATCH v3 09/13] pcie upstream port: pci express switch
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] Re: [PATCH v3 09/13] pcie upstream port: pci express switch upstream port. |
Date: |
Wed, 22 Sep 2010 13:22:15 +0200 |
User-agent: |
Mutt/1.5.20 (2009-12-10) |
On Wed, Sep 15, 2010 at 02:38:22PM +0900, Isaku Yamahata wrote:
> pci express switch upstream port.
>
> Signed-off-by: Isaku Yamahata <address@hidden>
> ---
> Changes v2 -> v3:
> - compilation adjustment.
This is in fact a specific upstream port, isn't it?
If so rename all PCIE names here to specific port model?
Also, this is small enough to avoid splitting it out
from the switch code: if we don't, we won't have
APIs like pcie_upstream_init which is only useful
as part of switch.
> ---
> Makefile.objs | 2 +-
> hw/pcie_upstream.c | 200
> ++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pcie_upstream.h | 32 ++++++++
> 3 files changed, 233 insertions(+), 1 deletions(-)
> create mode 100644 hw/pcie_upstream.c
> create mode 100644 hw/pcie_upstream.h
>
> diff --git a/Makefile.objs b/Makefile.objs
> index 7e81b57..72ca8be 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -139,7 +139,7 @@ user-obj-y += cutils.o cache-utils.o
> hw-obj-y =
> hw-obj-y += vl.o loader.o
> hw-obj-y += virtio.o virtio-console.o
> -hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o pci_bridge.o
> +hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o pci_bridge.o
> pcie_upstream.o
> hw-obj-y += watchdog.o
> hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
> hw-obj-$(CONFIG_ECC) += ecc.o
> diff --git a/hw/pcie_upstream.c b/hw/pcie_upstream.c
> new file mode 100644
> index 0000000..a08fce1
> --- /dev/null
> +++ b/hw/pcie_upstream.c
> @@ -0,0 +1,200 @@
> +/*
> + * pcie_upstream.c
> + *
> + * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "pci_ids.h"
> +#include "msi.h"
> +#include "pcie.h"
> +#include "pcie_upstream.h"
> +
> +/* For now, TI XIO3130 is borrowed. need to get its own id? */
> +#define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */
> +#define XIO3130_REVISION 0x2
> +#define XIO3130_MSI_OFFSET 0x70
> +#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
> +#define XIO3130_MSI_NR_VECTOR 1
> +#define XIO3130_SSVID_OFFSET 0x80
> +#define XIO3130_SSVID_SVID 0
> +#define XIO3130_SSVID_SSID 0
> +#define XIO3130_EXP_OFFSET 0x90
> +#define XIO3130_AER_OFFSET 0x100
> +
> +#define PCIE_UPSTREAM_VID PCI_VENDOR_ID_TI
> +#define PCIE_UPSTREAM_DID PCI_DEVICE_ID_TI_XIO3130U
> +#define PCIE_UPSTREAM_REVISION XIO3130_REVISION
> +#define PCIE_UPSTREAM_MSI_SUPPORTED_FLAGS XIO3130_MSI_SUPPORTED_FLAGS
> +#define PCIE_UPSTREAM_MSI_NR_VECTOR XIO3130_MSI_NR_VECTOR
> +#define PCIE_UPSTREAM_MSI_OFFSET XIO3130_MSI_OFFSET
> +#define PCIE_UPSTREAM_SSVID_OFFSET XIO3130_SSVID_OFFSET
> +#define PCIE_UPSTREAM_SVID XIO3130_SSVID_SVID
> +#define PCIE_UPSTREAM_SSID XIO3130_SSVID_SSID
> +#define PCIE_UPSTREAM_EXP_OFFSET XIO3130_EXP_OFFSET
> +#define PCIE_UPSTREAM_AER_OFFSET XIO3130_AER_OFFSET
> +
> +static void pcie_upstream_write_config(PCIDevice *d,
> + uint32_t address, uint32_t val, int
> len)
> +{
> + uint32_t uncorsta =
> + pci_get_long(d->config + pcie_aer_cap(d) + PCI_ERR_UNCOR_STATUS);
> +
> + pci_bridge_write_config(d, address, val, len);
> + pcie_cap_flr_write_config(d, address, val, len);
> + msi_write_config(d, address, val, len);
> + pcie_aer_write_config(d, address, val, len, uncorsta);
> +}
> +
> +static void pcie_upstream_reset(DeviceState *qdev)
> +{
> + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> + msi_reset(d);
> + pci_bridge_reset(qdev);
> + pcie_cap_deverr_reset(d);
> +}
> +
> +static void pcie_upstream_flr(PCIDevice *d)
> +{
> + /* TODO: not enabled until qdev reset clean up
> + waiting for Anthony's qdev cealn up */
> +#if 0
> + /* So far, sticky bit registers or register which must be preserved
> + over FLR aren't emulated. So just reset this device. */
> + pci_device_reset(d);
> +#endif
> +}
> +
> +static int pcie_upstream_initfn(PCIDevice *d)
> +{
> + PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
> + PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
> + int rc;
> +
> + rc = pci_bridge_initfn(d);
> + if (rc < 0) {
> + return rc;
> + }
> +
> + pcie_port_init_reg(d);
> + pci_config_set_vendor_id(d->config, PCIE_UPSTREAM_VID);
> + pci_config_set_device_id(d->config, PCIE_UPSTREAM_DID);
> + d->config[PCI_REVISION_ID] = PCIE_UPSTREAM_REVISION;
> +
> + rc = msi_init(d, PCIE_UPSTREAM_MSI_OFFSET, PCIE_UPSTREAM_MSI_NR_VECTOR,
> + PCIE_UPSTREAM_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
> + PCIE_UPSTREAM_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
> + if (rc < 0) {
> + return rc;
> + }
> + rc = pci_bridge_ssvid_init(d, PCIE_UPSTREAM_SSVID_OFFSET,
> + PCIE_UPSTREAM_SVID, PCIE_UPSTREAM_SSID);
> + if (rc < 0) {
> + return rc;
> + }
> + rc = pcie_cap_init(d, PCIE_UPSTREAM_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
> + p->port);
> + if (rc < 0) {
> + return rc;
> + }
> + pcie_cap_flr_init(d, &pcie_upstream_flr);
> + pcie_cap_deverr_init(d);
> + pcie_aer_init(d, PCIE_UPSTREAM_AER_OFFSET);
> +
> + return 0;
> +}
> +
> +static int pcie_upstream_exitfn(PCIDevice *d)
> +{
> + pcie_aer_exit(d);
> + msi_uninit(d);
> + pcie_cap_exit(d);
> + return pci_bridge_exitfn(d);
> +}
> +
> +PCIEPort *pcie_upstream_init(PCIBus *bus, int devfn, bool multifunction,
> + const char *bus_name, pci_map_irq_fn map_irq,
> + uint8_t port)
> +{
> + PCIDevice *d;
> + PCIBridge *br;
> + DeviceState *qdev;
> +
> + d = pci_create_multifunction(bus, devfn, multifunction,
> + PCIE_UPSTREAM_PORT);
> + if (!d) {
> + return NULL;
> + }
> + br = DO_UPCAST(PCIBridge, dev, d);
> +
> + qdev = &br->dev.qdev;
> + pci_bridge_map_irq(br, bus_name, map_irq);
> + qdev_prop_set_uint8(qdev, "port", port);
> + qdev_init_nofail(qdev);
> +
> + return DO_UPCAST(PCIEPort, br, br);
> +}
> +
> +static const VMStateDescription vmstate_pcie_upstream = {
> + .name = "pcie-upstream-port",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
> + VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
> + PCIE_AERLog),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static PCIDeviceInfo pcie_upstream_info = {
> + .qdev.name = PCIE_UPSTREAM_PORT,
> + .qdev.desc = "Upstream Port of PCI Express Switch",
> + .qdev.size = sizeof(PCIEPort),
> + .qdev.reset = pcie_upstream_reset,
> + .qdev.vmsd = &vmstate_pcie_upstream,
> +
> + .is_express = 1,
> + .is_bridge = 1,
> + .config_write = pcie_upstream_write_config,
> + .init = pcie_upstream_initfn,
> + .exit = pcie_upstream_exitfn,
> +
> + .qdev.props = (Property[]) {
> + DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
> + DEFINE_PROP_UINT16("aer_log_max", PCIEPort,
> br.dev.exp.aer_log.log_max,
> + PCIE_AER_LOG_MAX_DEFAULT),
> + DEFINE_PROP_END_OF_LIST(),
> + }
> +};
> +
> +static void pcie_upstream_register(void)
> +{
> + pci_qdev_register(&pcie_upstream_info);
> +}
> +
> +device_init(pcie_upstream_register);
> +
> +
> +/*
> + * Local variables:
> + * c-indent-level: 4
> + * c-basic-offset: 4
> + * tab-width: 8
> + * indent-tab-mode: nil
> + * End:
> + */
> diff --git a/hw/pcie_upstream.h b/hw/pcie_upstream.h
> new file mode 100644
> index 0000000..1d36317
> --- /dev/null
> +++ b/hw/pcie_upstream.h
> @@ -0,0 +1,32 @@
> +/*
> + * pcie_upstream.h
> + *
> + * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
There's nothing
> +
> +#ifndef QEMU_PCIE_UPSTREAM_H
> +#define QEMU_PCIE_UPSTREAM_H
> +
> +#include "pcie_port.h"
> +
> +#define PCIE_UPSTREAM_PORT "pcie-upstream-port"
> +
> +PCIEPort *pcie_upstream_init(PCIBus *bus, int devfn, bool multifunction,
> + const char *bus_name, pci_map_irq_fn map_irq,
> + uint8_t port);
> +
> +#endif /* QEMU_PCIE_UPSTREAM_H */
> --
> 1.7.1.1
- [Qemu-devel] [PATCH v3 12/13] pcie/aer: glue aer error injection into qemu monitor., (continued)
[Qemu-devel] [PATCH v3 09/13] pcie upstream port: pci express switch upstream port., Isaku Yamahata, 2010/09/15
- [Qemu-devel] Re: [PATCH v3 09/13] pcie upstream port: pci express switch upstream port.,
Michael S. Tsirkin <=
[Qemu-devel] [PATCH v3 11/13] pcie/hotplug: glue pushing attention button command. pcie_abp, Isaku Yamahata, 2010/09/15
[Qemu-devel] [PATCH v3 13/13] msix: clear not only INTA, but all INTx when MSI-X is enabled., Isaku Yamahata, 2010/09/15
[Qemu-devel] [PATCH v3 04/13] pcie: add pcie constants to pcie_regs.h, Isaku Yamahata, 2010/09/15
[Qemu-devel] [PATCH v3 06/13] pcie/aer: helper functions for pcie aer capability., Isaku Yamahata, 2010/09/15