[Qemu-devel] Re: [PATCH v4 05/15] pci/bridge: fix pci_bridge_reset()

[Michael S. Tsirkin]

On Mon, Oct 18, 2010 at 12:17:46PM +0900, Isaku Yamahata wrote:
> lower 4bits of base/limit register is RO, and
> should not be modified on reset.
> 
> Signed-off-by: Isaku Yamahata <address@hidden>
> ---
>  hw/pci_bridge.c |   15 +++++++++------
>  1 files changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
> index 638e3b3..7229610 100644
> --- a/hw/pci_bridge.c
> +++ b/hw/pci_bridge.c
> @@ -161,12 +161,15 @@ void pci_bridge_reset_reg(PCIDevice *dev)
>      conf[PCI_SUBORDINATE_BUS] = 0;
>      conf[PCI_SEC_LATENCY_TIMER] = 0;
>  
> -    conf[PCI_IO_BASE] = 0;
> -    conf[PCI_IO_LIMIT] = 0;
> -    pci_set_word(conf + PCI_MEMORY_BASE, 0);
> -    pci_set_word(conf + PCI_MEMORY_LIMIT, 0);
> -    pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0);
> -    pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0);
> +    pci_clear_bit_byte(conf + PCI_IO_BASE, PCI_IO_RANGE_MASK & 0xff);
> +    pci_clear_bit_byte(conf + PCI_IO_LIMIT, PCI_IO_RANGE_MASK & 0xff);

No need for & 0xff and & 0xfffff here and below.

also, PCI spec also says that these registers' value
is undefined after reset, so no need to clear them?
If there's a reason, pls put it in comment.


> +    pci_clear_bit_word(conf + PCI_MEMORY_BASE, PCI_MEMORY_RANGE_MASK & 
> 0xffff);
> +    pci_clear_bit_word(conf + PCI_MEMORY_LIMIT,
> +                       PCI_MEMORY_RANGE_MASK & 0xffff);
> +    pci_clear_bit_word(conf + PCI_PREF_MEMORY_BASE,
> +                       PCI_PREF_RANGE_MASK & 0xffff);
> +    pci_clear_bit_word(conf + PCI_PREF_MEMORY_LIMIT,
> +                       PCI_PREF_RANGE_MASK & 0xffff);
>      pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
>      pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
>  
> -- 
> 1.7.1.1