[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Wed, Oct 20, 2010 at 07:36:37AM +0900, Isaku Yamahata wrote:
> On Tue, Oct 19, 2010 at 07:06:55PM +0200, Michael S. Tsirkin wrote:
> > On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
> > > On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
> > > > On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> > > > > On uncorrectable error status register in pcie_aer_write_config().
> > > > > The register is RW1CS, so making it writable and test-and-clear 
> > > > > doesn't
> > > > > work.
> > > > 
> > > > Sure. But isn't this what w1cmask implements?
> > > 
> > > It's not simple W1C.
> > 
> > Well it's also sticky, but this only affects reset.
> > What else is different?
> 
> The bit of uncorsta that corresponds to the first error:
>         If 1b is written, the side effects takes place.
>         If multiple header recording is disabled, the bit is W1C.
>         If multiple header recording is enabled, the bit may or may
>         not be cleared depending on whether recorded errors.
>         The next error header is pulled out from the internal log.
>         (the first error bit moves to the one that corresponds to
>          the pulled-out one.)
> 
> The other bits of uncorsta
>         If multiple header recording is disabled, the bit is W1C.
>         If multiple header recording is enabled, the value isn't cleared
>         even when 1b is written. So since we set w1cmask, we need to
>         restore the old value.

I think I suggested once a good way to implement this:

- always make the bits w1c
- after config write:
  if MHR is enabled, and you see that error log is not empty and that bit is 0,
  this means that someone has written 1b.
  so pop the first error from the log, and set bit to 1 if it's not empty.

This way we only touch w1c mask on setup, no tricky range checks.
Anything wrong with this approach?

-- 
MST