[Qemu-devel] [PATCH 7/7] pci bridge: implement secondary bus reset

[Isaku Yamahata]

Emulates secondary bus reset when secondary bus reset bit
is written from 0 to 1.

Signed-off-by: Isaku Yamahata <address@hidden>
Signed-off-by: Anthony Liguori <address@hidden>
---
 hw/pci_bridge.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index 58cc2e4..618a81e 100644
--- a/hw/pci_bridge.c
+++ b/hw/pci_bridge.c
@@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, 
uint8_t type)
 void pci_bridge_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len)
 {
+    PCIBridge *s = container_of(d, PCIBridge, dev);
+    uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
+    uint16_t bridge_control_new;
+
     pci_default_write_config(d, address, val, len);
 
     if (/* io base/limit */
@@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d,
         /* memory base/limit, prefetchable base/limit and
            io base/limit upper 16 */
         ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
-        PCIBridge *s = container_of(d, PCIBridge, dev);
         pci_bridge_update_mappings(&s->sec_bus);
     }
+
+    bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
+    if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) &&
+        (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) {
+        /* 0 -> 1 */
+        pci_bus_reset(&s->sec_bus);
+    }
 }
 
 void pci_bridge_disable_base_limit(PCIDevice *dev)
-- 
1.7.1.1