[Qemu-devel] [PATCH 3/4] linux-user: ARM: clear the IT bits when invoking a signal handler

[Peter Maydell]

When invoking a signal handler for an ARM target, make sure the IT
bits in the CPSR are cleared. (This would otherwise cause incorrect
execution if the IT state was non-zero when an exception occured.
This bug has been masked previously because we weren't getting the
IT state bits at exception entry right anyway.)

Also use the proper cpsr_read()/cpsr_write() interface to update
the CPSR rather than manipulating CPUState fields directly.

Signed-off-by: Peter Maydell <address@hidden>
---
 linux-user/signal.c |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/linux-user/signal.c b/linux-user/signal.c
index c846b8c..0664770 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -1256,6 +1256,14 @@ setup_return(CPUState *env, struct target_sigaction *ka,
        abi_ulong handler = ka->_sa_handler;
        abi_ulong retcode;
        int thumb = handler & 1;
+       uint32_t cpsr = cpsr_read(env);
+
+       cpsr &= ~CPSR_IT;
+       if (thumb) {
+               cpsr |= CPSR_T;
+       } else {
+               cpsr &= ~CPSR_T;
+       }
 
        if (ka->sa_flags & TARGET_SA_RESTORER) {
                retcode = ka->sa_restorer;
@@ -1278,13 +1286,7 @@ setup_return(CPUState *env, struct target_sigaction *ka,
        env->regs[13] = frame_addr;
        env->regs[14] = retcode;
        env->regs[15] = handler & (thumb ? ~1 : ~3);
-       env->thumb = thumb;
-
-#if 0
-#ifdef TARGET_CONFIG_CPU_32
-       env->cpsr = cpsr;
-#endif
-#endif
+       cpsr_write(env, cpsr, 0xffffffff);
 
        return 0;
 }
-- 
1.7.1